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MU9C16K64M-50B568C PDF预览

MU9C16K64M-50B568C

更新时间： 2024-02-14 20:30:02
品牌 Logo 应用领域
MUSIC 存储内存集成电路静态存储器双倍数据速率
页数 文件大小 规格书
35页 1040K
描述
MU9C RCP Family

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MU9C16K64M-50B568C 技术参数

是否Rohs认证：不符合生命周期：Contact Manufacturer
包装说明：BGA, BGA568,26X26,50Reach Compliance Code：unknown
风险等级：5.88Is Samacsys：N
最长访问时间：50 nsJESD-30 代码：S-PBGA-B568
JESD-609代码：e0内存密度：1048576 bit
内存集成电路类型：CONTENT ADDRESSABLE SRAM内存宽度：64
端子数量：568字数：16384 words
字数代码：16000最高工作温度：70 °C
最低工作温度：组织：16KX64
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA568,26X26,50封装形状：SQUARE
封装形式：GRID ARRAY电源：3.3 V
认证状态：Not Qualified最大待机电流：0.005 A
子类别：SRAMs最大压摆率：0.9 mA
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
Base Number Matches：1

MU9C16K64M-50B568C 数据手册

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MU9C RCP Family  
Packet Stream  
Controller  
Switch Control  
And Packet  
Data  
Switch  
Fabric  
RCP  
Control  
Network  
Address  
Data  
RAM  
Address  
MU9C  
RAM  
Figure 2: Switch Block Diagram  
PIN DESCRIPTIONS  
Note: Signal names that start with a slash ("/") are active LOW. All signals are 3.3V CMOS level. Never leave inputs floating. The CAM  
architecture draws substantial currents during compare operations, mandating the use of good layout and bypassing techniques. Refer  
to the Electrical Characteristics section for more information.  
DQ31-0 (Data Bus, Three-state, Common  
Input/ Output)  
DSC (Data Segment Control, Input)  
When DQ bus access to a 64 bit register or memory word  
is performed, the DSC input determines whether bits 31-0  
(DSC LOW) or bits 63-32 (DSC HIGH) are accessed.  
Access to 32 bit registers require that DSC be held LOW.  
The DQ31-0 lines convey data to and from the MU9C  
RCP. When the /E input is HIGH the DQ31-0 lines are  
held in their high-impedance state. The /W input deter-  
mines whether data flows to or from the device on the  
DQ31-0 lines. The source or destination of the data is  
determined by the AC bus, DSC, and the /AV line. During  
a Write cycle, data on the DQ31-0 lines is registered by the  
falling edge of /E.  
AA12-0/AA11-0 (Active Address, Output)  
The AA bus conveys the Match address, the Next Free  
address, or Random Access address, depending on the  
most recent memory cycle. The /OE input enables the AA  
bus; when the /OE input is HIGH, the AA bus is in its  
high-impedance state; when /OE is LOW the AA bus is  
active. In a vertically cascaded system after a Comparison  
cycle, Write at Next Free Address cycle or Read/Write at  
Highest-Priority match, only the highest-priority device  
will enable its AA bus, regardless of the state of the /OE  
input. In the event of a mismatch in the Address Database  
after a Compare cycle, or after a Write at Next Free  
Address cycle into an already full system, the lowest-pri-  
ority device will drive the AA bus with all 1s. The AA bus  
is latched when /E is LOW, and are free to change only  
when /E is HIGH.  
AC12-0/AC11-0 (Address/Control Bus, Input)  
When Hardware control is selected, the AC bus conveys  
address or control information to the MU9C RCP, depend-  
ing on the state of the /AV input. When /AV is LOW then  
the AC bus carries an address; when /AV is HIGH the AC  
bus carries control information. Data on the AC bus is reg-  
istered by the falling edge of /E. When software control is  
selected, the state of the AC bus does not affect the opera-  
tion of the device.  
Rev. 8.04  
3
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