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MTS1512K8C12LSJ2B PDF预览

MTS1512K8C12LSJ2B

更新时间： 2024-11-11 05:04:47
品牌 Logo 应用领域
MICROSS 静态存储器内存集成电路
页数 文件大小 规格书
10页 448K
描述
Standard SRAM, 512KX8, 12ns, CMOS, CDSO36, CERAMIC, SOJ-36

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MTS1512K8C12LSJ2B 数据手册

 浏览型号MTS1512K8C12LSJ2B的Datasheet PDF文件第2页浏览型号MTS1512K8C12LSJ2B的Datasheet PDF文件第3页浏览型号MTS1512K8C12LSJ2B的Datasheet PDF文件第4页浏览型号MTS1512K8C12LSJ2B的Datasheet PDF文件第5页浏览型号MTS1512K8C12LSJ2B的Datasheet PDF文件第6页浏览型号MTS1512K8C12LSJ2B的Datasheet PDF文件第7页 
PRELIMINARY  
MTS1512K8CxxLSJ2  
4Mb Monolithic SRAM  
PIN DIAGRAM  
4Mb, 512K x 8, Asynchronous, Low  
Power SRAM Memory Array  
PIN SIGNAL NAME  
PIN SIGNAL NAME  
1
2
3
4
5
6
36  
35  
34  
33  
32  
31  
A0  
NC  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
2
A1  
A18  
A17  
A16  
A15  
OE\  
IO 7  
IO 6  
VSS  
VCC  
IO 5  
IO 4  
A14  
A13  
A12  
A11  
A10  
NC  
AVAILABILITY:  
3
A2  
4
A3  
DSCC SMD 5962-95600  
QML-Q Compliant  
Mil 883 Compliant  
5
A4  
CE\  
IO 0  
IO 1  
VCC  
VSS  
IO 2  
IO 3  
WE\  
A5  
A6  
A7  
A8  
A9  
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
7
8
9
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
10  
11  
12  
13  
14  
15  
16  
17  
18  
FEATURES:  
High Speed, Asynchronous operation  
Fully Static, No Clocks required  
Center Power & Ground for improved noise  
immunity  
Easy Memory Array expansion with use of Chip  
Select (CS\) and Output Enable (OE\)  
All Inputs/Outputs are TTL compatible  
Low Power with Data Retention Functionality  
Product Access Speed Options:  
FUNCTIONAL BLOCK  
o
15, 17, 20, 25, 35 and 45ns  
Package Option:  
36LD-CSOJ  
o
FUNCTIONAL DESCRIPTION  
INPUT BUFFER  
The MTS1512K8C is a high-performance Low Power  
CMOS Static Random Access Memory (SRAM),  
organized as 512K words by 8-bits wide, containing a  
total density of 512K bytes. Memory expansion is easily  
achieved through use of the Chip-Select (CS\) and  
Output Enable (OE\) control inputs along with the tri-  
state output drivers. Writing to the device is  
accomplished by driving CS\ and WE\ LOW. Data on  
the eight IO pins (IO0-IO7) is then written into the  
addressed location specified on the Address Input pins  
(A0-A18).  
IO 0  
IO 1  
IO 2  
IO 3  
IO 4  
IO 5  
IO 6  
IO 7  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
512K x 8  
Asynchronous  
SRAM  
ARRAY  
2048 Rows  
2048 Columns  
POWER  
DOWN  
CE\  
WE\  
COLUMN DECODE  
OE\  
Reading from the MTS1512K8C is accomplished by  
driving Chip Select (CS\) and Output Enable (OE\) LOW,  
while forcing Write Enable (WE\) HIGH. Under these  
stimulus conditions, the contents of the addressed  
memory location (A0-A18) will be available on the  
Output pins (IO0-IO7).  
MAXIMUM RATINGS  
PARAMETER  
Operating Temperature  
Storage Temperature  
SYMBOL  
LIMIT  
UNITS  
˚C  
-55 to +125  
-65 to 150  
TA  
TSTG  
VS  
The MTS1512K8C is placed into an inactive, High-  
Impedance state when the device has been de-selected  
by driving Chip-Select (CS\) HIGH. The eight Input-  
Output lines (IO0-IO7) are also in a High-Impedance  
state when the MTS1512K8C is placed into a WRITE  
operation by driving Chip-Select (CS\) and Write Enable  
(WE\) LOW. This device supports Low Voltage Data  
Retention.  
˚C  
Supply Voltage Relative to GND  
-0.5 to VCC+0.5  
V
DC Voltage applied to Outputs in  
High-Z  
-0.5 to VCC+0.5  
-0.5 to VCC+0.5  
V
V
VOZG  
VG  
DC Input Voltage  
MTS1512K8C-L - Rev 1.1 - 07/12  
Minco Technology Labs, LLC reserves the right to change products or specification without notice.  
1234567...10

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