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MTB6N60ET4 PDF预览

MTB6N60ET4

更新时间: 2024-01-23 05:59:49
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 晶体管
页数 文件大小 规格书
10页 192K
描述
Power Field-Effect Transistor, 6A I(D), 600V, 1.2ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET

MTB6N60ET4 技术参数

生命周期:Obsolete包装说明:SMALL OUTLINE, R-PSSO-G2
Reach Compliance Code:unknownHTS代码:8541.29.00.95
风险等级:5.74外壳连接:DRAIN
配置:SINGLE最小漏源击穿电压:600 V
最大漏极电流 (ID):6 A最大漏源导通电阻:1.2 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PSSO-G2
元件数量:1端子数量:2
工作模式:ENHANCEMENT MODE封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
极性/信道类型:N-CHANNEL认证状态:Not Qualified
表面贴装:YES端子形式:GULL WING
端子位置:SINGLE晶体管元件材料:SILICON
Base Number Matches:1

MTB6N60ET4 数据手册

 浏览型号MTB6N60ET4的Datasheet PDF文件第2页浏览型号MTB6N60ET4的Datasheet PDF文件第3页浏览型号MTB6N60ET4的Datasheet PDF文件第4页浏览型号MTB6N60ET4的Datasheet PDF文件第6页浏览型号MTB6N60ET4的Datasheet PDF文件第7页浏览型号MTB6N60ET4的Datasheet PDF文件第8页 
12  
300  
200  
100  
V
= 300 V  
= 6 A  
= 10 V  
= 25°C  
DD  
Q
T
I
V
T
D
GS  
10  
8
J
V
GS  
Q
Q
2
t
1
10  
d(off)  
6
4
t
t
f
r
100  
0
t
d(on)  
I
T
= 6 A  
= 25°C  
D
J
2
0
Q
V
3
DS  
1
1
10  
100  
0
6
12  
18  
24  
30  
36  
Q , TOTAL CHARGE (nC)  
R
, GATE RESISTANCE (OHMS)  
T
G
Figure 8. Gate–To–Source and Drain–To–Source  
Voltage versus Total Charge  
Figure 9. Resistive Switching Time  
Variation versus Gate Resistance  
DRAIN–TO–SOURCE DIODE CHARACTERISTICS  
6
V
= 0 V  
GS  
= 25  
T
°C  
J
5
4
3
2
1
0
0.50  
0.55  
0.60  
0.65  
0.70  
0.75  
0.80  
0.85  
V
, SOURCE–TO–DRAIN VOLTAGE (VOLTS)  
SD  
Figure 10. Diode Forward Voltage versus Current  
SAFE OPERATING AREA  
The Forward Biased Safe Operating Area curves define  
the maximum simultaneous drain–to–source voltage and  
drain current that a transistor can handle safely when it is for-  
ward biased. Curves are based upon maximum peak junc-  
able operation, the stored energy from circuit inductance dis-  
sipated in the transistor while in avalanche must be less than  
the rated limit and adjusted for operating conditions differing  
from those specified. Although industry practice is to rate in  
terms of energy, avalanche energy capability is not a con-  
stant. The energy rating decreases non–linearly with an in-  
crease of peak current in avalanche and peak junction  
temperature.  
tion temperature and a case temperature (T ) of 25°C. Peak  
C
repetitive pulsed power limits are determined by using the  
thermal response data in conjunction with the procedures  
discussed in AN569, “Transient Thermal Resistance–Gener-  
al Data and Its Use.”  
Although many E–FETs can withstand the stress of drain–  
to–source avalanche at currents up to rated pulsed current  
Switching between the off–state and the on–state may tra-  
verse any load line provided neither rated peak current (I  
)
DM  
) is exceeded and the transition time  
(I  
), the energy rating is specified at rated continuous cur-  
DM  
nor rated voltage (V  
DSS  
rent (I ), in accordance with industry custom. The energy rat-  
D
(t ,t ) do not exceed 10 µs. In addition the total power aver-  
r f  
ing must be derated for temperature as shown in the  
accompanying graph (Figure 12). Maximum energy at cur-  
aged over a complete switching cycle must not exceed  
(T  
– T )/(R ).  
J(MAX)  
C
θJC  
rents below rated continuous I can safely be assumed to  
A Power MOSFET designated E–FET can be safely used  
D
in switching circuits with unclamped inductive loads. For reli-  
Motorola TMOS Power MOSFET Transistor Device Data  
equal the values indicated.  
5

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