Datasheet > MT89L80AN1

MT89L80AN1

更新时间： 2024-01-31 02:42:21

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		电信集成电路光电二极管
页数	文件大小	规格书
17页	350K
描述
CMOS ST-BUSTM Family

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技术参数
数据手册

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MT89L80AN1 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	SSOP,	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.83
JESD-30 代码：	R-PDSO-G48	JESD-609代码：	e3
长度：	15.88 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	48
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	2.79 mm	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	DIGITAL TIME SWITCH	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	7.49 mm

MT89L80AN1 数据手册

MT89L80

Data Sheet

(unused)

Mode

Control

Bits

Memory

Select

Bits

Stream

Address

Bits

Bit

Name

Description

Message When 1, the contents of the Connection Memory Low are output on the Serial Output

Mode

streams except when the ODE pin is low. When 0, the Connection Memory bits for each

channel determine what is output.

(unused)

Memory

4-3

0-0 - Not to be used

Select Bits 0-1 - Data Memory (read only from the microprocessor port)

1-0 - Connection Memory Low

1-1 - Connection Memory High

2-0

Stream

The number expressed in binary notation on these bits refers to the input or output ST-BUS

Address Bits stream which corresponds to the subsection of memory made accessible for subsequent

operations.

Figure 4 - Control Register Bits

No Corresponding Memory

- These bits give 0s if read.

Per Channel

Control Bits

Bit

Name

Description

Message When 1, the contents of the corresponding location in Connection Memory Low are

Channel output on the location’s channel and stream. When 0, the contents of the corresponding

location in Connection Memory Low act as an address for the Data Memory and so

determine the source of the connection to the location’s channel and stream.

CSTo Bit This bit is output on the CSTo pin one channel early. The CSTo bit for stream 0 is output

first.

Output

Enable

If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the

output driver for the location’s channel and stream. This allows individual channels on

individual streams to be made high-impedance, allowing switching matrices to be

constructed. A 1 enables the driver and a 0 disables it.

Figure 5 - Connection Memory High Bits

Zarlink Semiconductor Inc.

1...3 4 567 8 9...17

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