Datasheet > MT89L80AN1

MT89L80AN1

更新时间： 2024-01-11 14:17:26

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		电信集成电路光电二极管
页数	文件大小	规格书
17页	350K
描述
CMOS ST-BUSTM Family

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MT89L80AN1 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	SSOP,	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.83
JESD-30 代码：	R-PDSO-G48	JESD-609代码：	e3
长度：	15.88 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	48
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	2.79 mm	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	DIGITAL TIME SWITCH	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	7.49 mm

MT89L80AN1 数据手册

MT89L80

Data Sheet

Pin Description (continued)

Pin #

Name

Description

PLCC SSOP

14 15

C4i

4.096 MHz Clock (5 V-tolerant Input). ST-BUS bit cell boundaries lie on the alternate

falling edges of this clock.

15-17 16-18

19-21 20-22

A0-2 Address 0-2 / Input Streams 8-10 (5 V-tolerant Input). These are the inputs for the

address lines on the microprocessor interface.

A3-5 Address 3-5 / Input Streams 11-13 (5 V-tolerant Input). These are the inputs for the

address lines on the microprocessor interface.

Data Strobe (5 V-tolerant Input). This is the input for the active high data strobe on the

microprocessor interface.

R/W Read/Write (5 V-tolerant Input). This is the input for the read/write signal on the

microprocessor interface - high for read, low for write.

Chip Select (5 V-tolerant Input). This is the input for the active low chip select on the

microprocessor interface

25-27 27-29 D7-D5 Data Bus (5 V-tolerant I/O): These are the bidirectional data pins on the

microprocessor interface.

29-33 31-35 D4-D0 Data Bus (5 V-tolerant I/O): These are the bidirectional data pins on the

microprocessor interface.

V_SS

Ground.

25,37

35-39 38-42 STo7-3 ST-BUS Outputs 7 to 3 (5 V-Tolerant Three-state Outputs). These are the pins for the

eight 2048 kbit/s ST-BUS output streams.

41-43 44-46 STo2-0 ST-BUS Outputs 2to 0 (5 V-Tolerant Three-state Outputs). These are the pins for the

eight 2048kbit/s ST-BUS output streams.

ODE Output Drive Enable (5 V-tolerant Input). If this input is held high, the STo0-STo7

output drivers function normally. If this input is low, the STo0-STo7 output drivers go into

their high impedance state. NB: Even when ODE is high, channels on the STo0-STo7

outputs can go high impedance under software control.

CSTo Control ST-BUS Output (5 V-Tolerant Output). Each frame of 256 bits on this ST-BUS

output contains the values of bit 1 in the 256 locations of the Connection Memory High.

6, 18, 6, 19,

28, 40 30, 43

No Connection.

Functional Description

In recent years, there has been a trend in telephony towards digital switching, particularly in association with

software control. Simultaneously, there has been a trend in system architectures towards distributed processing or

multi-processor systems.

In accordance with these trends, Zarlink has devised the ST-BUS (Serial Telecom Bus). This bus architecture can

be used both in software-controlled digital voice and data switching, and for interprocessor communications. The

uses in switching and in interprocessor communications are completely integrated to allow for a simple general

purpose architecture appropriate for the systems of the future.

Zarlink Semiconductor Inc.

1 234 5 6 7...17

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