Datasheet > MT89L80

MT89L80

更新时间： 2024-01-30 01:21:10

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		/
页数	文件大小	规格书
17页	350K
描述
CMOS ST-BUSTM Family

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MT89L80 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QCCJ, LDCC44,.7SQ	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.2
JESD-30 代码：	S-PQCC-J44	JESD-609代码：	e0
长度：	16.585 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	44
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC44,.7SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	225
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	4.57 mm	子类别：	Other Telecom ICs
最大压摆率：	0.01 mA	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	DIGITAL TIME SWITCH	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	16.585 mm
Base Number Matches：	1

MT89L80 数据手册

MT89L80

Data Sheet

Stream

Address

Bits

Channel

Address

Bits

Bit

Name

Description

The number expressed in binary notation on these 3 bits is the number of the ST-BUS

7-5*

Stream

Address stream for the source of the connection. Bit 7 is the most significant bit. e.g., if bit 7 is 1,

Bits*

bit 6 is 0 and bit 5 is 0, then the source of the connection is a channel on STi4.

4-0*

Channel The number expressed in binary notation on these 5 bits is the number of the channel

Address which is the source of the connection (The ST-BUS stream where the channel lies is

Bits*

defined by bits 7, 6 and 5.). Bit 4 is the most significant bit. e.g., if bit 4 is 1, bit 3 is 0, bit 2

is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.

*If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire

8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated

to define the source of the connection which is output on the channel and stream associated with this location.

Figure 6 - Connection Memory Low Bits

If bit 6 of the Control Register is 0, then bits 2 and 0 of each Connection Memory High location function normally

(see Fig. 5). If bit 2 is 1, the associated ST-BUS output channel is in Message Mode; i.e., the byte in the

corresponding Connection Memory Low location is transmitted on the stream at that channel. Otherwise, one of the

bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low define the ST-

BUS input stream and channel where the byte is to be found (see Fig. 6).

If the ODE pin is low, then all serial outputs are high-impedance. If it is high and bit 6 in the Control Register is 1,

then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is 0, then the bit 0 in the

Connection Memory High location enables the output drivers for the corresponding individual ST-BUS output

stream and channel. Bit 0=1 enables the driver and bit 0=0 disables it (see Fig. 5).

Bit 1 of each Connection Memory High location (see Fig. 5) is output on the CSTo pin once every frame. To allow for

delay in any external control circuitry the bit is output one channel before the corresponding channel on the ST-BUS

streams, and the bit for stream 0 is output first in the channel; e.g., bit 1’s for channel 9 of streams 0-7 are output

synchronously with ST-BUS channel 8 bits 7-0.

Applications

Use in a Simple Digital Switching System

Figs. 7 and 8 show how MT89L80s can be used with MT8964s to form a simple digital switching system. Fig. 7

shows the interface between the MT89L80s and the filter/codecs. Fig. 8 shows the position of these components in

an example architecture.

The MT8964 filter/codec in Fig. 7 receives and transmits digitized voice signals on the ST-BUS input D_R, and ST-

BUS output D_X, respectively. These signals are routed to the ST-BUS inputs and outputs on the top MT89L80,

which is used as a digital speech switch.

The MT8964 is controlled by the ST-BUS input D_Coriginating from the bottom MT89L80, which generates the

appropriate signals from an output channel in Message Mode. This architecture optimizes the messaging capability

Zarlink Semiconductor Inc.

1...4 5 678 9 10...17

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MT89L80AN1	ZARLINK	CMOS ST-BUSTM Family	获取价格
MT89L80ANR	ZARLINK	CMOS ST-BUSTM Family	获取价格
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