Datasheet > MT89L80

MT89L80

更新时间： 2024-01-12 04:48:16

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		/
页数	文件大小	规格书
17页	350K
描述
CMOS ST-BUSTM Family

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MT89L80 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QCCJ, LDCC44,.7SQ	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.2
JESD-30 代码：	S-PQCC-J44	JESD-609代码：	e0
长度：	16.585 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	44
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC44,.7SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	225
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	4.57 mm	子类别：	Other Telecom ICs
最大压摆率：	0.01 mA	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	DIGITAL TIME SWITCH	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	16.585 mm
Base Number Matches：	1

MT89L80 数据手册

MT89L80

Data Sheet

Hex Address

Location

•

00 - 1F

Control Register *

•

Channel 0^†

Channel 1^†

•

Channel 31^†

* Writing to the Control Register is the only fast transaction.

^†Memory and stream are specified by the contents of the Control Register.

Figure 3 - Address Memory Map

Software Control

The address lines on the Control Interface give access to the Control Register directly or, depending on the

contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory.

If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If

A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory

and stream selected in the Control Register.

The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see

Fig. 4). The memory select bits allow the Connection Memory High or Low or the Data Memory to be chosen, and

the stream address bits define one of the ST-BUS input or output streams.

Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are to the

Connection Memory Low.

The other mode control bit, bit 6, puts every output channel on every output stream into active Message Mode; i.e.,

the contents of the Connection Memory Low are output on the ST-BUS output streams once every frame unless the

ODE pin is low. In this mode the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1,

regardless of the actual values.

(unused)

Mode

Control

Bits

Memory

Select

Bits

Stream

Address

Bits

Bit

Name

Description

Split Memory When 1, all subsequent reads are from the Data Memory and writes are to the Connection

Memory Low, except when the Control Register is accessed again. When 0, the Memory

Select bits specify the memory for subsequent operations. In either case, the Stream

Address Bits select the subsection of the memory which is made available.

Zarlink Semiconductor Inc.

1 2 3 456 7 8...17

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MT89L80AN	MITEL	CMOS ST-BUS⑩ FAMILY Digital Switch	获取价格
MT89L80AN	ZARLINK	CMOS ST-BUSTM Family	获取价格
MT89L80AN1	ZARLINK	CMOS ST-BUSTM Family	获取价格
MT89L80ANR	ZARLINK	CMOS ST-BUSTM Family	获取价格
MT89L80ANR1	ZARLINK	CMOS ST-BUSTM Family	获取价格
MT89L80AP	ZARLINK	CMOS ST-BUSTM Family	获取价格

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