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MT8979 PDF预览

MT8979

更新时间: 2024-11-17 10:43:51
品牌 Logo 应用领域
加拿大卓联 - ZARLINK PC
页数 文件大小 规格书
34页 628K
描述
CEPT PCM 30/CRC-4 Frame & Interface

MT8979 数据手册

 浏览型号MT8979的Datasheet PDF文件第2页浏览型号MT8979的Datasheet PDF文件第3页浏览型号MT8979的Datasheet PDF文件第4页浏览型号MT8979的Datasheet PDF文件第5页浏览型号MT8979的Datasheet PDF文件第6页浏览型号MT8979的Datasheet PDF文件第7页 
ISO-CMOS ST-BUSTM Family  
CEPT PCM 30/CRC-4 Frame & Interface  
MT8979  
Data Sheet  
February 2005  
Features  
Single chip primary rate 2048 kbit/s CEPT  
Ordering Information  
transceiver with CRC-4 option  
MT8979AE  
MT8979AP  
MT8979APR  
MT8979AE1  
MT8979AP1  
28 Pin PDIP  
44 Pin PLCC  
44 Pin PLCC  
28 Pin PDIP*  
44 Pin PLCC*  
Tubes  
Meets CCITT Recommendation G.704  
Selectable HDB3 or AMI line code  
Tx and Rx frame and multiframe synchronization  
signals  
Tubes  
Tape & Reel  
Tubes  
Tubes  
MT8979APR1 44 Pin PLCC*  
*Pb Free Matte Tin  
Tape & Reel  
Two frame elastic buffer with 32 µsec jitter buffer  
Frame alignment and CRC error counters  
-40°C to +85°C  
Insertion and detection of A, B, C, D signalling  
bits with optional debounce  
Description  
The MT8979 is a single chip CEPT digital trunk  
transceiver that meets the requirements of CCITT  
On-chip attenuation ROM with option for ADI  
codecs  
Recommendation  
equipment.  
G.704  
for  
digital  
multiplex  
Per channel, overall and remote loop around  
ST-BUS compatible  
The MT8979 is fabricated in Zarlink’s low power ISO-  
CMOS technology.  
Applications  
Primary rate ISDN network nodes  
Multiplexing equipment  
Private network: PBX to PBX links  
High speed computer to computer links  
VDD  
RxD  
TxMF  
C2i  
F0i  
ST-BUS  
Timing  
2 Frame  
Circuitry  
Elastic Buffer  
with Slip  
RxMF  
Digital  
RxA  
Remote  
&
Attenuator  
Control  
RxB  
TxA  
TxB  
ROM  
DSTi  
Digital  
Loop-  
backs  
CEPT  
Link  
PCM/Data  
Interface  
DSTo  
ADI  
Interface  
CSTi0  
CSTi1  
CSTo  
Serial  
Control  
Interface  
ABCD Bit RAM  
Phase  
Detector  
E2i  
E8Ko  
CEPT  
Counter  
XCtl  
XSt  
Control Logic  
VSS  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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