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MT8980DP PDF预览

MT8980DP

更新时间: 2024-11-20 04:14:15
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信集成电路电信转换电路电信电路PC
页数 文件大小 规格书
20页 483K
描述
ISO-CMOS ST-BUS Family Digital Switch

MT8980DP 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:QCCJ, LDCC44,.7SQReach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.55
JESD-30 代码:S-PQCC-J44JESD-609代码:e0
长度:16.585 mm湿度敏感等级:1
功能数量:1端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC44,.7SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Other Telecom ICs
最大压摆率:0.01 mA标称供电电压:5 V
表面贴装:YES技术:CMOS
电信集成电路类型:DIGITAL TIME SWITCH温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:16.585 mm
Base Number Matches:1

MT8980DP 数据手册

 浏览型号MT8980DP的Datasheet PDF文件第2页浏览型号MT8980DP的Datasheet PDF文件第3页浏览型号MT8980DP的Datasheet PDF文件第4页浏览型号MT8980DP的Datasheet PDF文件第5页浏览型号MT8980DP的Datasheet PDF文件第6页浏览型号MT8980DP的Datasheet PDF文件第7页 
ISO-CMOS ST-BUSTM Family  
MT8980D  
Digital Switch  
Data Sheet  
February 2005  
Features  
Zarlink ST-BUS compatible  
8-line x 32-channel inputs  
Ordering Information  
MT8980DE  
MT8980DP  
40 Pin PDIP  
44 Pin PLCC  
44 Pin PLCC  
44 Pin PLCC*  
40 Pin PDIP*  
44 Pin PLCC*  
Tubes  
Tubes  
8-line x 32-channel outputs  
256 ports non-blocking switch  
Single power supply (+5 V)  
Low power consumption: 30 mW Typ.  
Microprocessor-control interface  
Three-state serial outputs  
MT8980DPR  
MT8980DP1  
MT8980DE1  
MT8980DPR1  
Tape & Reel  
Tubes  
Tubes  
Tape & Reel  
*Pb Free Matte Tin  
-40°C to +85°C  
Description  
This VLSI ISO-CMOS device is designed for switching  
PCM-encoded voice or data, under microprocessor  
control, in a modern digital exchange, PBX or Central  
Office. It provides simultaneous connections for up to  
256 64 kbit/s channels. Each of the eight serial inputs  
and outputs consist of 32 64 kbit/s channels  
multiplexed to form a 2048 kbit/s ST-BUS stream. In  
addition, the MT8980 provides microprocessor read  
and write access to individual ST-BUS channels.  
VDD VSS  
ODE  
F0i  
C4i  
Frame  
Counter  
Output  
MUX  
STo0  
STo1  
STo2  
STo3  
STo4  
STo5  
STo6  
STo7  
STi0  
STi1  
Parallel  
to  
Serial  
Serial  
to  
Parallel  
Converter  
Data  
Memory  
STi2  
STi3  
STi4  
STi5  
STi6  
STi7  
Control Register  
Converter  
Connection  
Memory  
Control Interface  
DS CS R/W A5/ DTA D7/  
CSTo  
A0  
D0  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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