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MT8972BP PDF预览

MT8972BP

更新时间: 2024-10-27 22:51:03
品牌 Logo 应用领域
MITEL 网络接口电信集成电路综合业务数字网
页数 文件大小 规格书
20页 393K
描述
ISO2-CMOS ST-BUS⑩ FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit

MT8972BP 数据手册

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MT8971B/72B  
Pin Description (continued)  
Pin #  
Name  
Description  
DIP PLCC  
17  
22  
OSC1  
Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical  
Characteristics for OSC1 input requirements.  
18  
23  
Precan Precanceller Disable. When held to Logic ’1’, the internal path from LOUT to the  
precanceller is forced to VBias thus bypassing the precanceller section. When logic ’0’, the  
L
OUT to the precanceller path is enabled and functions normally. An internal pulldown (50  
k) is provided on this pin.  
1,6,  
11,  
18,  
20,  
25  
NC  
No Connection. Leave open circuit.  
19  
24  
LOUT DIS LOUT Disable. When held to logic “1”, LOUT is disabled (i.e., output = VBias). When logic  
“0”, LOUT functions normally. An internal pulldown (50 k) is provided on this pin.  
20  
21  
22  
26  
27  
28  
TEST  
LIN  
Test Pin. Connect to VSS for normal operation.  
Receive Signal input (Analog).  
VDD  
Positive Power Supply (+5V) input.  
F0  
C4  
B17  
B17  
B16  
B16  
B15  
B15  
B14  
B14  
B13  
B13  
B12  
B12  
B11  
B11  
B10  
B10  
B17  
B17  
DSTi  
DSTo  
F0o  
Channel Time 0  
Figure 3 - DV Port - 80 kbit/s (Modes 2, 3, 6)  
F0  
C4  
B17  
DSTi  
B17 B16 B15 B14 B13 B12 B11 B10  
B17 B16 B15 B14 B13 B12 B11 B10  
B27 B26 B25 B24 B23 B22 B21 B20  
B27 B26 B25 B24 B23 B22 B21 B20  
DSTo  
F0o  
B17  
Channel Time 0  
Channel Time 16  
Figure 4 - DV Port - 160 kbit/s (Modes 2, 3, 6)  
9-109  

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