Datasheet > MT58L128V32P1T-4IT

MT58L128V32P1T-4IT

更新时间： 2023-02-26 15:05:40

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
27页	447K
描述
Standard SRAM, 128KX32, 2.3ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100

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PRELIMINARY

4Mb : 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

TQFP PIN DESCRIPTIONS (co n t in u e d )

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

ADSC#

Input Synchronous Address Status Controller: This active LOW input

interrupts any ongoing burst, causing a new external address to be

registered. A READ or WRITE is performed using the new address if

CE# is LOW. ADSC# is also used to place the chip into power-down

state when CE# is HIGH.

MODE

Input Mode: This input selects the burst sequence. A LOW on this pin

selects “linear burst.” NC or HIGH on this pin selects “interleaved

burst.” Do not alter input state while device is operating.

Input Snooze Enable: This active HIGH, asynchronous input causes the

device to enter a low-power standby mode in which all data in the

memory array is retained. When ZZ is active, all other inputs are

ignored.

(a) 58, 59,

62, 63, 68, 69, 56-59, 62, 63

72, 73

(b) 8, 9, 12,

13, 18, 19, 22, 72-75, 78, 79

(a) 52, 53,

DQa

DQb

Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte “b”

Output is DQb pins. For the x32 and x36 versions, Byte “a” is DQa pins;

Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins.

Input data must meet setup and hold times around the rising edge

of CLK.

(b) 68, 69

12, 13

(d) 18, 19,

22-25, 28, 29

DQc

DQd

–

NC/DQPa

NC/DQPb

NC/DQPc

NC/DQPd

NC/

I/O

No Connect/Parity Data I/Os: On the x32 version, these pins are No

Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”

parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte

“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.

–

14, 15, 41, 65, 14, 15, 41, 65,

91 91

Supply Power Supply: See DC Electrical Characteristics and Operating

Conditions for range.

4, 11, 20, 27, 4, 11, 20, 27,

54, 61, 70, 77 54, 61, 70, 77

Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and

Operating Conditions for range.

5, 10, 17, 21, 5, 10, 17, 21,

26, 40, 55, 60, 26, 40, 55, 60,

67, 71, 76, 90 67, 71, 76, 90

Supply Ground: GND.

38, 39

DNU

–

Do Not Use: These signals may either be unconnected or wired to

GND to improve package heat dissipation.

1-3, 6, 7, 16,

25, 28-30,

16, 66

No Connect: These signals are not internally connected and may be

connected to ground to improve package heat dissipation.

51-53, 56, 57,

66, 75, 78, 79,

95, 96

42, 43

–

No Function: These pins are internally connected to the die and

have the capacitance of input pins. It is allowable to leave these

pins unconnected or driven by signals. Reserved for address

expansion; pin 43 becomes an SA at 8Mb density and pin 42

becomes an SA at 16Mb density.

4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM

MT58L256L18P1.p65 – Rev. 3/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1...4 5 678 9 10...27

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MT58L128V32P1T-5IT	CYPRESS	Cache SRAM, 128KX32, 3.1ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100	获取价格
MT58L128V32P1T-6	CYPRESS	Cache SRAM, 128KX32, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100	获取价格
MT58L128V32P1T-7.5	CYPRESS	Cache SRAM, 128KX32, 4ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100	获取价格
MT58L128V32P1T-7.5IT	CYPRESS	Standard SRAM, 128KX32, 4ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100	获取价格
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