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MT58L128V36F1T-6.8 PDF预览

MT58L128V36F1T-6.8

更新时间: 2023-08-15 00:00:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
26页 447K
描述
Cache SRAM, 128KX36, 6.8ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

MT58L128V36F1T-6.8 数据手册

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4Mb: 256K x 18, 128K x 32/36  
FLOW-THROUGH SYNCBURST SRAM  
4Mb SYNCBURST™  
SRAM  
MT58L256L18F1, MT58L128L32F1,  
MT58L128L36F1; MT58L256V18F1,  
MT58L128V32F1, MT58L128V36F1  
3.3V VDD, 3.3V or 2.5V I/O, Flow-Through  
FEATURES  
1
100-PinTQFP  
• Fast clock and OE# access times  
• Single +3.3V +0.3V/-0.165V power supply (VDD)  
• Separate +3.3V or +2.5V isolated output buffer  
supply (VDDQ)  
• SNOOZE MODE for reduced-power standby  
• Common data inputs and data outputs  
• Individual BYTE WRITE control and GLOBAL WRITE  
• Three chip enables for simple depth expansion  
and address pipelining  
• Clock-controlled and registered addresses, data  
I/Os and control signals  
• Internally self-timed WRITE cycle  
• Burst control pin (interleaved or linear burst)  
• Automatic power-down  
• 165-pin FBGA package  
• 100-pin TQFP package  
• Low capacitive bus loading  
165-PinFBGA  
• x18, x32, and x36 versions available  
OPTIONS  
MARKING  
• Timing (Access/Cycle/MHz)  
6.8ns/7.5ns/133 MHz  
7.5ns/8.8ns/113 MHz  
8.5ns/10ns/100 MHz  
10ns/15ns/66 MHz  
-6.8  
-7.5  
-8.5  
-10  
• Configurations  
3.3V I/O  
256K x 18  
128K x 32  
128K x 36  
2.5V I/O  
MT58L256L18F1  
MT58L128L32F1  
MT58L128L36F1  
NOTE: 1. JEDEC-standardMS-026BHA(LQFP).  
256K x 18  
128K x 32  
128K x 36  
MT58L256V18F1  
MT58L128V32F1  
MT58L128V36F1  
GENERALDESCRIPTION  
The Micron® SyncBurstSRAM family employs  
high-speed, low-power CMOS designs that are fabri-  
cated using an advanced CMOS process.  
• Packages  
100-pin TQFP  
165-pin FBGA  
T
F*  
Micron’s 4Mb SyncBurst SRAMs integrate a 256K x  
18, 128K x 32, or 128K x 36 SRAM core with advanced  
synchronous peripheral circuitry and a 2-bit burst  
counter. All synchronous inputs pass through registers  
controlled by a positive-edge-triggered single clock in-  
put (CLK). The synchronous inputs include all ad-  
dresses, all data inputs, active LOW chip enable (CE#),  
two additional chip enables for easy depth expansion  
(CE2#, CE2), burst control inputs (ADSC#, ADSP#,  
ADV#), byte write enables (BWx#) and global write  
(GW#).  
• Operating Temperature Range  
Commercial (0°C to +70°C)  
None  
IT  
Industrial (-40°C to +85°C)**  
Part Number Example:  
MT58L256L18F1T-8.5  
* A Part Marking Guide for the FBGA devices can be found on Micron’s  
Web site—http://www.micron.com/support/index.html.  
** Industrial temperature range offered in specific speed grades and  
configurations. Contact factory for more information.  
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM  
MT58L256L18F1_F.p65 – Rev. F, Pub. 1/03 EN  
©2003,MicronTechnology,Inc.  
1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.  

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