PRELIMINARY
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
GENERALDESCRIPTION
The Micron® SyncBurst™ SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
internally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls
DQb pins and DQPb. During WRITE cycles on the x32
and x36 devices, BWa# controls DQa pins and DQPa;
BWb# controls DQb pins and DQPb; BWc# controls
DQc pins and DQPc; BWd# controls DQd pins and
DQPd. GW# LOW causes all bytes to be written. Parity
bits are only available on the x18 and x36 versions.
Micron’s 4Mb SyncBurst SRAMs operate from a
+3.3V VDD power supply, and all inputs and outputs are
TTL-compatible. Users can choose either a 2.5V or 3.3V
I/O version. The device is ideally suited for 486,
Pentium®, and PowerPC systems and those systems
that benefit from a wide synchronous data bus. The
device is also ideal in generic 16-, 18-, 32-, 36-, 64-, and
72-bit-wide applications.
Micron’s 4Mb SyncBurst SRAMs integrate a 256K x
18, 128K x 32, or 128K x 36 SRAM core with advanced
synchronousperipheralcircuitryanda2-bitburstcounter.
All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input
(CLK). The synchronous inputs include all addresses, all
data inputs, active LOW chip enable (CE#), two addi-
tional chip enables for easy depth expansion (CE2#,
CE2), burst control inputs (ADSC#, ADSP#, ADV#), byte
write enables (BWx#) and global write (GW#).
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is also
a burst mode input (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can
be from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
PleaserefertoMicron’sWebsite(www.micron.com/
products/datasheets/syncds.html) for the latest data
sheet.
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
x18
NC
NC
NC
x32/x36
NC/DQPc*
DQc
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
x32/x36
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x18
NC
NC
NC
x32/x36
NC/DQPa*
DQa
PIN #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
x18
x32/x36
VSS
VSS
VDDQ
VDDQ
DQc
NC
NC
NC
DQd
DQd
NC/DQPd*
MODE
DQa
NC
NC
SA
DQb
DQb
NC/DQPb*
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
VDDQ
VSS
VDDQ
VSS
NC
NC
DQb
DQb
DQc
DQc
DQc
DQc
NC
NC
DQa
DQa
SA
SA
SA
DQa
DQa
VSS
VDDQ
DQa
DQa
ZZ
VDD
NC
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
VDDQ
SA
SA1
SA0
DNU
DNU
VSS
VDD
NF**
NF**
SA
DQb
DQb
DQc
DQc
VSS
VDD
NC
VSS
VSS
VDD
CE2#
BWa#
BWb#
DQb
DQb
DQd
DQd
DQa
DQa
DQb
DQb
VDDQ
VSS
SA
SA
SA
SA
SA
SA
VDDQ
VSS
NC
NC
BWc#
BWd#
DQb
DQb
DQPb
NC
DQd
DQd
DQd
DQd
DQa
DQa
DQPa
NC
DQb
DQb
DQb
DQb
CE2
CE#
SA
SA
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_C.p65 – Rev. 6/01
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2001,MicronTechnology,Inc.
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