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MT58L128L32D1B-5IT PDF预览

MT58L128L32D1B-5IT

更新时间： 2024-02-10 22:06:40
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
23页 605K
描述
Standard SRAM, 128KX32, 2.8ns, CMOS, PBGA119, 14 X 22 MM, BGA-119

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MT58L128L32D1B-5IT 技术参数

生命周期：Transferred零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.44
最长访问时间：2.8 nsJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：4718592 bit
内存集成电路类型：STANDARD SRAM内存宽度：36
功能数量：1端子数量：100
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX36
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

MT58L128L32D1B-5IT 数据手册

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PRELIMINARY  
4Mb : 256K x 18, 128K x 32/36  
3.3V I/O PIPELINED, DCD SYNCBURST SRAM  
TQFP PIN DESCRIPTIONS  
x18  
x32/x36  
SYMBOL TYPE  
DESCRIPTION  
37  
36  
37  
36  
SA0  
SA1  
SA  
Input Synchronous Address Inputs: These inputs are registered and must  
meet the setup and hold times around the rising edge of CLK.  
32-35, 44-50, 32-35, 44-50,  
80-82, 99,  
100  
81, 82, 99,  
100  
93  
94  
–
93  
94  
95  
96  
BWa#  
BWb#  
BWc#  
BWd#  
Input Synchronous Byte Write Enables: These active LOW inputs allow  
individual bytes to be written and must meet the setup and hold  
times around the rising edge of CLK. A byte write enable is LOW  
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,  
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and  
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and  
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins  
and DQPc; BWd# controls DQd pins and DQPd. Parity is only  
available on the x18 and x36 versions.  
–
87  
88  
89  
87  
88  
89  
BWE#  
GW#  
CLK  
Input Byte Write Enable: This active LOW input permits BYTE WRITE  
operations and must meet the setup and hold times around the  
rising edge of CLK.  
Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit  
WRITE to occur independent of the BWE# and BWx# lines and must  
meet the setup and hold times around the rising edge of CLK.  
Input Clock: This signal registers the address, data, chip enable, byte write  
enables and burst control inputs on its rising edge. All synchronous  
inputs must meet setup and hold times around the clock’s rising  
edge.  
98  
92  
64  
98  
92  
64  
CE#  
CE2#  
ZZ  
Input Synchronous Chip Enable: This active LOW input is used to enable  
the device and conditions the internal use of ADSP#. CE# is sampled  
only when a new external address is loaded.  
Input Synchronous Chip Enable: This active LOW input is used to enable  
the device and is sampled only when a new external address is  
loaded.  
Input Snooze Enable: This active HIGH, asynchronous input causes the  
device to enter a low-power standby mode in which all data in the  
memory array is retained. When ZZ is active, all other inputs are  
ignored.  
97  
97  
CE2  
Input Synchronous Chip Enable: This active HIGH input is used to enable  
the device and is sampled only when a new external address is  
loaded.  
86  
83  
86  
83  
OE#  
Input Output Enable: This active LOW, asynchronous input enables the  
data I/O output drivers.  
ADV#  
Input Synchronous Address Advance: This active LOW input is used to  
advance the internal burst counter, controlling burst access after  
the external address is loaded. A HIGH on this pin effectively causes  
wait states to be generated (no address advance). To ensure use of  
correct address during a WRITE cycle, ADV# must be HIGH at the  
rising edge of the first clock after an ADSP# cycle is initiated.  
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM  
MT58L256L18D1.p65 – Rev 12/99  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
5
©1999, Micron Technology, Inc.  
12345678...23

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