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MT58L128L32D1B-5IT PDF预览

MT58L128L32D1B-5IT

更新时间： 2024-02-17 20:43:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
23页 605K
描述
Standard SRAM, 128KX32, 2.8ns, CMOS, PBGA119, 14 X 22 MM, BGA-119

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MT58L128L32D1B-5IT 技术参数

生命周期：Transferred零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.44
最长访问时间：2.8 nsJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：4718592 bit
内存集成电路类型：STANDARD SRAM内存宽度：36
功能数量：1端子数量：100
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX36
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

MT58L128L32D1B-5IT 数据手册

 浏览型号MT58L128L32D1B-5IT的Datasheet PDF文件第1页浏览型号MT58L128L32D1B-5IT的Datasheet PDF文件第2页浏览型号MT58L128L32D1B-5IT的Datasheet PDF文件第4页浏览型号MT58L128L32D1B-5IT的Datasheet PDF文件第5页浏览型号MT58L128L32D1B-5IT的Datasheet PDF文件第6页浏览型号MT58L128L32D1B-5IT的Datasheet PDF文件第7页 
PRELIMINARY  
4Mb : 256K x 18, 128K x 32/36  
3.3V I/O PIPELINED, DCD SYNCBURST SRAM  
GENERAL DESCRIPTION (co n t in u e d )  
Asynchronous inputs include the output enable  
(OE#), clock (CLK) and snooze enable (ZZ). There is also  
a burst mode input (MODE) that selects between inter-  
leaved and linear burst modes. The data-out (Q), en-  
abled by OE#, is also asynchronous. WRITE cycles can  
be from one to two bytes wide (x18) or from one to four  
bytes wide (x32/x36), as controlled by the write control  
inputs.  
devices, BWa# controls DQa’s and DQPa; BWb# con-  
trols DQb’s and DQPb; BWc# controls DQc’s and DQPc;  
BWd# controls DQd’s and DQPd. GW# LOW causes all  
bytes to be written. Parity bits are only available on the  
x18 and x36 versions.  
This device incorporates an additional pipelined  
enable register which delays turning off the output  
buffer an additional cycle when a deselect is executed.  
This feature allows depth expansion without penaliz-  
ing system performance.  
Micron’s 4Mb SyncBurst SRAMs operate from a  
+3.3V VDD power supply, and all inputs and outputs are  
TTL-compatible. The device is ideally suited for  
Pentium® and PowerPC pipelined systems and systems  
that benefit from a very wide, high-speed data bus. The  
device is also ideal in generic 16-, 18-, 32-, 36-, 64- and  
72-bit-wide applications.  
Burst operation can be initiated with either address  
status processor (ADSP#) or address status controller  
(ADSC#) inputs. Subsequent burst addresses can be  
internally generated as controlled by the burst advance  
input (ADV#).  
Address and write control are registered on-chip to  
simplify WRITE cycles. This allows self-timed WRITE  
cycles. Individual byte enables allow individual bytes  
to be written. During WRITE cycles on the x18 device,  
BWa# controls DQa’s and DQPa; BWb# controls DQb’s  
and DQPb. During WRITE cycles on the x32 and x36  
PleaserefertoMicron’sWebsite(www.micron.com/  
mti/msp/html/sramprod.html)forthelatestdatasheet.  
TQFP PIN ASSIGNMENT TABLE  
PIN #  
1
2
3
4
5
6
7
8
x18  
NC  
NC  
NC  
x32/x36  
NC/DQPc*  
DQc  
PIN #  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
x18  
x32/x36  
VSS  
VDDQ  
DQd  
DQd  
NC/DQPd*  
MODE  
PIN #  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
x18  
NC  
NC  
NC  
x32/x36  
NC/DQPa*  
DQa  
PIN #  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
x18  
x32/x36  
VSS  
VDDQ  
DQb  
DQb  
NC/DQPb*  
SA  
SA  
ADV#  
ADSP#  
ADSC#  
OE#  
BWE#  
GW#  
CLK  
DQc  
NC  
NC  
NC  
DQa  
NC  
NC  
SA  
VDDQ  
VSS  
VDDQ  
VSS  
NC  
NC  
DQb  
DQb  
DQc  
DQc  
DQc  
DQc  
NC  
NC  
DQa  
DQa  
SA  
SA  
SA  
DQa  
DQa  
VSS  
VDDQ  
DQa  
DQa  
ZZ  
VDD  
NC  
VSS  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
VSS  
VDDQ  
SA  
SA1  
SA0  
DNU  
DNU  
VSS  
VDD  
NF**  
NF**  
SA  
DQb  
DQb  
DQc  
DQc  
VDD  
VDD  
NC  
VSS  
VDD  
VSS  
CE2#  
BWa#  
BWb#  
DQb  
DQb  
DQd  
DQd  
DQa  
DQa  
DQb  
DQb  
VDDQ  
VSS  
SA  
SA  
SA  
SA  
SA  
SA  
VDDQ  
VSS  
NC  
NC  
BWc#  
BWd#  
DQb  
DQb  
DQPb  
NC  
DQd  
DQd  
DQd  
DQd  
DQa  
DQa  
DQPa  
NC  
DQb  
DQb  
DQb  
DQb  
CE2  
CE#  
SA  
SA  
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.  
**Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively.  
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM  
MT58L256L18D1.p65 – Rev 12/99  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©1999, Micron Technology, Inc.  
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