Datasheet > MT58L128L18PF-7.5IT

MT58L128L18PF-7.5IT

更新时间： 2024-02-28 19:15:58

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
25页	460K
描述
Standard SRAM, 128KX18, 4ns, CMOS, PBGA165, FBGA-165

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2Mb : 128K x 18, 64K x 32/36

PIPELINED, SCD SYNCBURST SRAM

TQFP PIN DESCRIPTIONS (co n t in u e d )

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

ADSC#

Input SynchronousAddressStatusController:ThisactiveLOWinput

interrupts any ongoing burst, causing a new external address to be

registered. A READ or WRITE is performed using the new address if

CE# is LOW. ADSC# is also used to place the chip into power-down

state when CE# is HIGH.

MODE

Input Mode: This input selects the burst sequence. A LOW on this pin

selects “linear burst.” NC or HIGH on this pin selects “interleaved

burst.” Do not alter input state while device is operating.

Input Snooze Enable: This active HIGH, asynchronous input causes the

device to enter a low-power standby mode in which all data in the

memory array is retained. When ZZ is active, all other inputs are

ignored.

(a) 58, 59,

62, 63, 68, 69, 56-59, 62, 63

72, 73

(a) 52, 53,

DQa

DQb

Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated with

Output DQa pins; Byte “b” is associated with DQb pins. For the x32 and x36

versions, Byte “a” is associated with DQa pins; Byte “b” is

associated with DQb pins; Byte “c” is associated with DQc pins;

Byte “d” is associated with DQd pins. Input data must meet setup

and hold times around the rising edge

(b) 8, 9, 12,

(b) 68, 69,

13, 18, 19, 22, 72-75, 78, 79

of CLK.

12, 13

DQc

(d) 18, 19,

22-25, 28, 29

DQd

–

NC/DQPa

NC/DQPb

NC/DQPc

NC/DQPd

NC/

I/O

No Connect/Parity Data I/Os: On the x32 version, these pins are No

Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”

parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte

“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.

–

14, 15, 41, 65, 14, 15, 41, 65,

91 91

VDD

Supply Power Supply: See DC Electrical Characteristics and Operating

Conditionsforrange.

4, 11, 20, 27, 4, 11, 20, 27,

54, 61, 70, 77 54, 61, 70, 77

VDDQ

Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and

OperatingConditionsforrange.

5, 10, 17, 21, 5, 10, 17, 21,

26, 40, 55, 60, 26, 40, 55, 60,

67, 71, 76, 90 67, 71, 76, 90

Supply Ground:GND.

38, 39, 42, 43 38, 39, 42, 43

DNU

–

Do Not Use: These signals may either be unconnected or wired to

GND to improve package heat dissipation.

1-3, 6, 7, 16,

25, 28-30,

16, 66

No Connect: These signals are not internally connected and may be

connectedtogroundtoimprovepackageheatdissipation.

51-53, 56, 57,

66, 75, 78, 79,

95, 96

NC/SA

–

No Connect: This pin is reserved for address expansion.

2Mb:128Kx18, 64Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L128L18P_2.p65 – Rev. 3/00

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

1...3 4 567 8 9...25

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与MT58L128L18PF-7.5IT相关器件

型号	品牌	获取价格	描述	数据表
MT58L128L18PT-10	CYPRESS	获取价格	Cache SRAM, 128KX18, 5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L128L18PT-10IT	CYPRESS	获取价格	Cache SRAM, 128KX18, 5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L128L18PT-10T	CYPRESS	获取价格	Cache SRAM, 128KX18, 5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100
MT58L128L18PT-5	CYPRESS	获取价格	Cache SRAM, 128KX18, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L128L18PT-5IT	CYPRESS	获取价格	Cache SRAM, 128KX18, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L128L18PT-6IT	CYPRESS	获取价格	Cache SRAM, 128KX18, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L128L18PT-6T	CYPRESS	获取价格	Cache SRAM, 128KX18, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100
MT58L128L18PT-7.5IT	CYPRESS	获取价格	Cache SRAM, 128KX18, 4ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L128L18PT-7.5T	CYPRESS	获取价格	Standard SRAM, 128KX18, 4ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100
MT58L128L32D1B-5	CYPRESS	获取价格	Standard SRAM, 128KX32, 2.8ns, CMOS, PBGA119, 14 X 22 MM, BGA-119

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