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MT28F642D18 PDF预览

MT28F642D18

更新时间: 2024-02-08 01:38:26
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镁光 - MICRON /
页数 文件大小 规格书
51页 584K
描述
FLASH MEMORY

MT28F642D18 数据手册

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ADVANCE  
4 MEG x 16  
ASYNC/PAGE/BURST FLASH MEMORY  
MT28F642D18  
MT28F642D20  
FLASH MEMORY  
Low Voltage, Extended Temperature  
0.18µm Process Technology  
FEATURES  
• Single device supports asynchronous, page, and  
burst operations  
PINASSIGNMENT  
59-BallFBGA  
• Flexible dual-bank architecture  
Support for true concurrent operation with zero  
latency  
Read bank a during program bank b and vice  
versa  
Read bank a during erase bank b and vice versa  
• Basic configuration:  
One hundred and thirty-five erasable blocks  
Bank a (16Mb for data storage)  
Bank b (48Mb for program storage)  
• VCC, VCCQ, VPP voltages  
1
2
3
4
5
6
7
8
A11  
A8  
V
SS  
VCC  
V
PP  
A18  
A6  
A4  
A
B
C
D
E
A12  
A13  
A15  
A9  
A20  
A21  
CLK  
ADV#  
A16  
RST#  
WE#  
DQ12  
DQ2  
A17  
A19  
WP#  
DQ1  
DQ9  
A5  
A7  
A3  
A2  
A10  
WAIT#  
DQ6  
A14  
A1  
V
CC  
Q
DQ15  
DQ14  
CE#  
DQ0  
DQ8  
A0  
DQ4  
1.70V (MIN), 1.90V (MAX) VCC, VCCQ  
(MT28F642D18 only)  
DQ13  
DQ5  
V
SS  
DQ10  
DQ3  
OE#  
F
DQ11  
1.80V (MIN), 2.20V (MAX) VCC, and  
2.25V (MAX) VCCQ (MT28F642D20 only)  
1.80V (TYP) VPP (in-system PROGRAM/ERASE)  
12V 5ꢀ (ꢁV) VPP tolerant (factory programming  
compatibility)  
DQ7  
V
SSQ  
V
CCQ  
VSSQ  
G
VCC  
Top View  
(Ball Down)  
1
• Random access time: 70ns @ 1.80V VCC  
NOTE: See page 7 for Ball Description Table.  
• Burst Mode read access  
See page 50 for mechanical drawing.  
MAX clock rate: 54 Mꢁz (tCLK = 18.5ns)  
Burst latency: 70ns @ 1.80V VCC and 54 Mꢁz  
tACLK: 15ns @ 1.80V VCC and 54 Mꢁz  
• Page Mode read access1  
• Cross-compatible command support  
Extended command set  
Four-/eight-word page  
Common flash interface  
Interpage read access: 70ns @ 1.80V  
Intrapage read access: 30ns @ 1.80V  
• Low power consumption (VCC = 2.20V)  
Asynchronous Read < 15mA  
• PROGRAM/ERASE cycle  
100,000 WRITE/ERASE cycles per block  
OPTIONS  
• Timing  
80ns access  
70ns access  
• Frequency  
40 Mꢁz  
54 Mꢁz  
• Boot Block Configuration  
Top  
Bottom  
• Package  
59-ball FBGA (8 x 7 ball grid)  
• Operating Temperature Range  
Extended (-40ºC to +85ºC)  
MARKING  
Interpage Read < 15mA  
Intrapage Read < 5mA  
Continuous Burst Read < 10mA  
WRITE < 55mA (MAX)  
ERASE < 45mA (MAX)  
-80  
-70  
4
5
Standby < 50µA (MAX)  
Automatic power save (APS) feature  
Deep power-down < 25µA (MAX)  
• Enhanced write and erase suspend options  
• Accelerated programming algorithm (APA) in-  
system and in-factory  
T
B
FN  
ET  
• Dual 64-bit chip protection registers for security  
purposes  
Part Number Example:  
MT28F642D20FN-804TET  
NOTE: 1. Data based on MT28F642D20 device.  
4Megx16Async/Page/BurstFlashMemory  
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02  
©2002,MicronTechnology,Inc.  
1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE  
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S  
PRODUCTIONDATASHEETSPECIFICATIONS.