Datasheet > MT28F1284W18

MT28F1284W18

更新时间： 2024-01-26 12:58:34

品牌	Logo	应用领域
镁光 - MICRON		/
页数	文件大小	规格书
66页	786K
描述
1.8V Low Voltage, Extended Temperature

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中文翻译

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数据手册

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MT28F1284W18 数据手册

8 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

MT28F1284W18

FLASH MEMORY

1.8V Lo w Vo lt a g e , Ext e n d e d Te m p e ra t u re

Fig u re 1: 56-Ba ll VFBGA

Fe a t u re s

Dedicated commands to decrease programming times for

both in-factory and in-system operations

Fast programming algorithm (FPA) for fast PROGRAM

operation

A11

VSS

VPP

A18

VCC

16-word page

Flexible 8Mb multipartition architecture

Single word (16-bit) data bus

Support for true concurrent operation with zero latency

Basic configuration:

A12

A13

A15

VCCQ

VSS

A20

A21

RST#

WE#

DQ12

DQ2

A17

A19

CLK

ADV#

A16

A10

A14

WAIT#

DQ6

A22

CE#

DQ0

DQ8

WP#

DQ1

DQ9

VCCQ

•

135 individually programmable/ erasable blocks

16 partitions (8Mb each for code and data storage)

DQ15

DQ14

VSSQ

DQ4

DQ11

VCC

Operating Voltage

DQ13

DQ5

DQ10

DQ3

OE#

VSSQ

•

VCC = 1.70V (MIN)–1.95V (MAX)

VCCQ = 1.70V (MIN)–2.24V (MAX)

DQ7

VPP = 1.8V (TYP) for in-system PROGRAM/ ERASE

•

12V ±5% (HV) VPP tolerant (factory programming

compatibility)

Top View

Random access time: 60ns @ 1.70V VCC

Burst mode read access

NOTE:

1. See Table 3 for ball descriptions.

2. See Figure 35 for mechanical drawing.

•

MAX clock rate: 66 MHz (^tCLK = 15ns)

MAX clock rate: 54 MHz (^tCLK = 18.5ns)

Burst latency 60ns @1.70V VCC and 66 MHz

4 word, 8 word, 16 word, and continuous burst modes

^tACLK: 14ns @ 1.70V VCC and 54 MHz

^tACLK: 11ns @ 1.70V VCC and 66 MHz

Op t io n s

Timing

Ma rkin g

Page mode read access

-60

-70

•

60ns access

70ns access

•

Interpage read access: 60ns @ 1.70V VCC

Intrapage read access: 15ns @ 1.70V VCC

Burst Frequency

Low power consumption (VCC = 1.95V)

•

54 MHz

•

Burst read @ 66 MHz <10mA (TYP)

Standby < 50µA(TYP)

Automatic power save (APS)

66 MHz¹

Boot Block Configuration

•

Top

Bottom

Enhanced program and erase suspend options

•

ERASE-SUSPEND-to-READ within same partition

PROGRAM-SUSPEND-to-READ within same

partition

Package

•

56-ball VFBGA (Standard) 7 x 8 ball

grid

•

ERASE-SUSPEND-to-PROGRAM within same

partition

•

56-ball VGBGA (Lead-free) 7 x 8 ball

grid²

Dual 64-bit chip protection registers for security purposes

Cross-compatible command support

Operating Temperature Range

Extended (-40ºC to +85ºC)

•

Extended command set

Common flash interface

NOTES: 1. Contact factory for availability.

2. Contact factory for details.

Programmable WAIT# configuration

Clock suspend

100,000 ERASE cycles per block

Part Number Example:

MT28F1284W18FQ-705 TET

09005aef80b425b4

MT28F1284W18_D.fm - Rev. D, 11/03 EN

^‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

12 3 4 5 6 7...66

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