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MT18VDDT12872AG PDF预览

MT18VDDT12872AG

更新时间: 2024-11-20 00:59:23
品牌 Logo 应用领域
镁光 - MICRON 动态存储器双倍数据速率
页数 文件大小 规格书
29页 679K
描述
DDR SDRAM UNBUFFERED DIMM

MT18VDDT12872AG 数据手册

 浏览型号MT18VDDT12872AG的Datasheet PDF文件第2页浏览型号MT18VDDT12872AG的Datasheet PDF文件第3页浏览型号MT18VDDT12872AG的Datasheet PDF文件第4页浏览型号MT18VDDT12872AG的Datasheet PDF文件第5页浏览型号MT18VDDT12872AG的Datasheet PDF文件第6页浏览型号MT18VDDT12872AG的Datasheet PDF文件第7页 
256MB, 512MB, 1GB (x72, ECC, DR), PC3200  
184-PIN DDR SDRAM UDIMM  
MT18VDDT3272A – 256MB  
MT18VDDT6472A – 512MB  
DDR SDRAM  
UNBUFFERED DIMM  
MT18VDDT12872A – 1GB  
For the latest data sheet, please refer to the MicronWeb  
site: www.micron.com/products/modules  
Fe a t u re s  
Fig u re 1: 184-Pin DIMM (MO-206)  
• 184-pin dual in-line memory module (DIMM)  
• Fast data transfer rates: PC3200  
• CAS Latency 3  
1.25in. (31.75mm)  
• Utilizes 400 MT/ s DDR SDRAM components  
• Supports ECC error detection and correction  
• 256MB (32 Meg x 72), 512MB (64 Meg x 72), and 1GB  
(128 Meg x 72)  
• VDD = VDDQ = +2.6V  
• VDDSPD = +2.3V to +3.6V  
• 2.6V I/ O (SSTL_2 compatible)  
• Com m ands entered on each positive CK edge  
• DQS edge-aligned with data for READs; center-  
aligned with data for WRITEs  
OPTIONS  
MARKING  
• Internal, pipelined double data rate (DDR)  
architecture; two data accesses per clock cycle  
• Package  
Bidirectional data strobe (DQS) transmitted/ received  
with data—i.e., source-synchronous data capture  
G
Y
184-pin DIMM (Standard)  
184-pin DIMM (Lead-free)  
• Memory Clock/ Speed, CAS Latency  
5ns (200MHz), 400MT/ s, CL = 3  
• PCB  
• Differential clock inputs CK and CK#  
• Four internal device banks for concurrent operation  
• Program m able burst lengths: 2, 4, or 8  
Auto precharge option  
-40B  
Standard 1.25in. (31.75mm)  
Auto Refresh and Self Refresh Modes  
• 15.6µs (256MB), 7.8125µs (512MB, 1GB) maximum  
average periodic refresh interval  
• Serial Presence Detect (SPD) with EEPROM  
• Programmable READ CAS latency  
• Gold edge contacts  
Ta b le 1:  
Ad d re ss Ta b le  
256MB  
512MB  
1GB  
8K  
4K  
8K  
Refresh Count  
4K (A0–A11)  
4 (BA0, BA1)  
128Mb (16 Meg x 8)  
1K (A0–A9)  
8K (A0–A12)  
4 (BA0, BA1)  
8K (A0–A12)  
4 (BA0, BA1)  
Row Addressing  
Device Bank Addressing  
Device Configuration  
Column Addressing  
Module Rank Addressing  
256Mb (32 Meg x 8)  
1K (A0–A9)  
512Mb (64 Meg x 8)  
2K (A0–A9, A11)  
2 (S0#, S1#)  
2 (S0#, S1#)  
2 (S0#, S1#)  
pdf: 09005aef80814e61, source: 09005aef80a43eed  
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN  
1
©2004 Micron Technology, Inc.  
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.  

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