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MT18VDVF6472D PDF预览

MT18VDVF6472D

更新时间: 2024-11-20 01:11:23
品牌 Logo 应用领域
镁光 - MICRON 动态存储器双倍数据速率
页数 文件大小 规格书
38页 719K
描述
DDR SDRAM VLP Registered DIMM

MT18VDVF6472D 数据手册

 浏览型号MT18VDVF6472D的Datasheet PDF文件第2页浏览型号MT18VDVF6472D的Datasheet PDF文件第3页浏览型号MT18VDVF6472D的Datasheet PDF文件第4页浏览型号MT18VDVF6472D的Datasheet PDF文件第5页浏览型号MT18VDVF6472D的Datasheet PDF文件第6页浏览型号MT18VDVF6472D的Datasheet PDF文件第7页 
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM  
Features  
DDR SDRAM VLP Registered DIMM  
MT18VDVF6472D – 512MB  
MT18VDVF12872D – 1GB  
For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/modules  
Figure 1:  
184-Pin VLP DIMM (MO-206)  
Features  
184-pin, very low profile dual in-line memory  
module (VLP DIMM)  
Very Low Profile Height 0.72in (18.29mm)  
Fast data transfer rates: PC2100 or PC2700  
Utilizes 266 MT/s and 333 MT/s DDR SDRAM  
components  
Registered inputs with one-clock delay  
Phase-lock loop (PLL) clock driver to reduce loading  
Supports ECC error detection and correction  
512MB (64 Meg x 72) and 1GB (128 Meg x 72)  
VDD = VDDQ = +2.5V  
Options  
Marking  
Package  
184-pin DIMM (standard)  
184-pin DIMM (lead-free)  
G
Y
VDDSPD = +2.3V to +3.6V  
2.5V I/O (SSTL_2 compatible)  
1
2
Memory clock, speed, CAS latency  
6ns (166MHz), 333 MT/s, CL = 2.5  
7.5ns (133 MHz), 266 MT/s, CL = 2  
7.5ns (133 MHz), 266 MT/s, CL = 2  
Commands entered on each positive CK edge  
DQS edge-aligned with data for READs; center-  
aligned with data for WRITEs  
Internal, pipelined double data rate (DDR)  
architecture; two data accesses per clock cycle  
Bidirectional data strobe (DQS) transmitted/  
received with data—i.e., source-synchronous data  
capture  
Differential clock inputs CK and CK#  
Four internal device banks for concurrent operation  
Programmable burst lengths: 2, 4, or 8  
Auto precharge option  
Auto refresh and self refresh modes  
7.8125µs maximum average periodic refresh  
interval  
-335  
1
-262  
1
-26A  
7.5ns (133 MHz), 266 MT/s, CL = 2.5  
PCB height  
-265  
1
Very Low-Profile 0.72in (18.29mm)  
Notes:1. Contact Micron for product availability.  
2. CL = CAS (READ) latency; registered mode  
adds one clock cycle to CL.  
Serial presence detect (SPD) with EEPROM  
Programmable READ CAS latency  
Gold edge contacts  
Dual rank  
PDF: 09005aef81c73825/Source: 09005aef81c73837  
DVF18C64_128x72D_1.fm - Rev. A 8/05 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.  
1
Products and specifications discussed herein are subject to change by Micron without notice.  

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