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MSC8144SVT800B PDF预览

MSC8144SVT800B

更新时间： 2024-11-29 18:13:15
品牌 Logo 应用领域
恩智浦 - NXP 时钟外围集成电路
页数 文件大小 规格书
80页 1499K
描述
133MHz, OTHER DSP, PBGA783, 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783

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中文翻译

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MSC8144SVT800B 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：BGA包装说明：BGA,
针数：783Reach Compliance Code：not_compliant
ECCN代码：5A992HTS代码：8542.31.00.01
风险等级：5.58桶式移位器：NO
边界扫描：YES最大时钟频率：133 MHz
格式：FIXED POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PBGA-B783JESD-609代码：e2
长度：29 mm低功率模式：NO
湿度敏感等级：3端子数量：783
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：245认证状态：Not Qualified
座面最大高度：3.176 mm最大供电电压：1.05 V
最小供电电压：0.97 V标称供电电压：1 V
表面贴装：YES技术：CMOS
端子面层：TIN SILVER端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：29 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

MSC8144SVT800B 数据手册

 浏览型号MSC8144SVT800B的Datasheet PDF文件第2页浏览型号MSC8144SVT800B的Datasheet PDF文件第3页浏览型号MSC8144SVT800B的Datasheet PDF文件第4页浏览型号MSC8144SVT800B的Datasheet PDF文件第5页浏览型号MSC8144SVT800B的Datasheet PDF文件第6页浏览型号MSC8144SVT800B的Datasheet PDF文件第7页 
Freescale Semiconductor  
Data Sheet  
Document Number: MSC8144  
Rev. 16, 5/2010  
MSC8144  
FC-PBGA–783  
29 mm × 29 mm  
Quad Core Digital Signal  
Processor  
•
Four StarCore® SC3400 DSP subsystems, each with an SC3400  
DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,  
memory management unit (MMU), extended programmable  
interrupt controller (EPIC), two general-purpose 32-bit timers,  
debug and profiling support, and low-power Wait and Stop  
processing modes.  
Chip-level arbitration and system (CLASS) that provides full  
fabric non-blocking arbitration between the processing elements  
and other initiators and the M2 memory, DDR SRAM controller,  
device configuration control and status registers, and other  
targets.  
128 Kbyte L2 shared instruction cache.  
512 Kbyte M2 memory for critical data and temporary data  
buffering.  
10 Mbyte 128-bit wide M3 memory.  
96 Kbyte boot ROM.  
Three input clocks (shared, global, and differential).  
Four PLLs (system, core, global, and serial RapidIO).  
DDR controller with up to a 200 MHz clock (400 MHz data rate),  
16/32 bit data bus, supporting up to 1 Gbyte in up to two banks  
and support for DDR1 and DDR2.  
DMA controller with 16 bidirectional channels with up to 1024  
buffer descriptors, and programmable priority, buffer, and  
multiplexing configuration.  
Up to eight independent TDM modules with programmable word  
size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,  
up to 128 Mbps data rate for all channels, with glueless interface  
to E1 or T1 framers, and can interface with H-MVIP/H.110  
devices, TSI, and codecs such as AC-97.  
– The two Ethernet controllers support 10/100/1000 Mbps  
operations via MII/RMII/SMII/RGMII/SGMII and the SGMII  
protocol using a 4-pin SerDes interface at 1000 Mbps data rate  
only.  
– The ATM controller supports UTOPIA level II 8/16 bits at  
25/50 MHz in UTOPIA/POS mode with adaptation layer  
support AAL0, AAL2, and AAL5.  
PCI designed to comply with the PCI specification revision 2.2 at  
33 MHz or 66 MHz with access to all PCI address spaces.  
Serial RapidIO® 1x/4x endpoint corresponds to Specification 1.2  
of the RapidIO trade association, and supports read, write,  
messages, doorbells, and maintenance accesses in inbound mode,  
and messages and doorbells in outbound mode.  
I/O interrupt concentrator consolidates all chip maskable interrupt  
and non-maskable interrupt sources and routes them to  
INT_OUT, NMI_OUT, and the cores.  
UART that permits full-duplex operation with a bit rate of up to  
6.25 Mbps.  
Serial peripheral interface (SPI).  
Four timer modules, each with four configurable16-bit timers.  
Four software watchdog timer (SWT) modules.  
Up to 32 general-purpose input/output (GPIO) ports, 16 of which  
can be configured as maskable interrupt inputs.  
I2C interface that allows booting from EEPROM devices.  
Eight programmable hardware semaphores.  
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Thirty two virtual maskable interrupts and one virtual NMI that  
can be generated by a simple write access.  
•
Optional booting via serial RapidIO port, PCI, I2C, SPI, or  
Ethernet interfaces.  
•
QUICC Engine™ technology subsystem with dual RISC  
processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction  
RAM, supporting three communication controllers with one ATM  
and two Gigabit Ethernet interfaces, to offload scheduling tasks  
from the DSP cores.  
Note: This document supports mask set M31H.  
© 2007–2010 Freescale Semiconductor, Inc.  
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