Datasheet > MSC7115VF1000

MSC7115VF1000

更新时间： 2024-01-15 21:43:16

品牌	Logo	应用领域
恩智浦 - NXP		时钟外围集成电路
页数	文件大小	规格书
56页	914K
描述
32-BIT, 266MHz, OTHER DSP, PBGA400, 17 X 17 MM, BGA-400

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MSC7115VF1000 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	BGA	包装说明：	17 X 17 MM, BGA-400
针数：	400	Reach Compliance Code：	not_compliant
ECCN代码：	3A001.A.3	HTS代码：	8542.31.00.01
风险等级：	5.79	地址总线宽度：	14
桶式移位器：	NO	位大小：	16
边界扫描：	YES	最大时钟频率：	266 MHz
外部数据总线宽度：	32	格式：	FIXED POINT
内部总线架构：	MULTIPLE	JESD-30 代码：	S-PBGA-B400
JESD-609代码：	e0	长度：	17 mm
低功率模式：	YES	湿度敏感等级：	3
端子数量：	400	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装等效代码：	BGA400,20X20,32	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH	电源：	1.2,2.5,3.3 V
认证状态：	Not Qualified	RAM（字数）：	196608
座面最大高度：	1.6 mm	子类别：	Digital Signal Processors
最大供电电压：	1.26 V	最小供电电压：	1.14 V
标称供电电压：	1.2 V	表面贴装：	YES
技术：	CMOS	端子面层：	Tin/Lead/Silver (Sn/Pb/Ag)
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	宽度：	17 mm
uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER	Base Number Matches：	1

MSC7115VF1000 数据手册

Freescale Semiconductor

Data Sheet

Document Number: MSC7115

Rev. 11, 4/2008

MSC7115

Low-Cost 16-bit DSP with

DDR Controller

MAP-BGA–400

17 mm × 17 mm

•

StarCore^®SC1400 DSP extended core with one SC1400 DSP

core, 192 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte

instruction cache (ICache), four-entry write buffer, programmable

interrupt controller (PIC), and low-power Wait and Stop

processing modes.

192 Kbyte M2 memory for critical data and temporary data

buffering.

8 Kbyte boot ROM.

•

Multi-channel DMA controller with 32 time-multiplexed

unidirectional channels, priority-based time-multiplexing

between channels using 32 internal priority levels, fixed- or

round-robin-priority operation, major-minor loop structure, and

DONE or DRACK protocol from requesting units.

Two independent TDM modules with independent receive and

transmit, programmable sharing of frame sync and clock,

programmable word size (8 or 16-bit), hardware-base

A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to

128 channels, with glueless interface to E1/T1 frames and MVIP,

SCAS, and H.110 buses.

UART with full-duplex operation up to 5.0 Mbps.

Up to 41 general-purpose input/output (GPIO) ports.

I²C interface that allows booting from EEPROM devices up to 1

Mbyte.

Two quad timer modules, each with sixteen configurable 16-bit

timers.

fieldBIST™ unit detects and provides visibility into unlikely field

failures for systems with high availability to ensure structural

integrity, that the device operates at the rated speed, is free from

reliability defects, and reports diagnostics for partial or complete

device inoperability.

Standard JTAG interface allows easy integration to system

firmware and internal on-chip emulation (OCE10) module.

Optional booting external host via 8-bit or 16-bit access through

the HDI16, I²C, or SPI using in the boot ROM to access serial SPI

Flash/EEPROM devices; different clocking options during boot

with the PLL on or off using a variety of input frequency ranges.

•

AHB-Lite crossbar switch that allows parallel data transfers

between four master ports and six slave ports, where each port

connects to an AHB-Lite bus; fixed or round robin priority

programmable at each slave port; programmable bus parking at

each slave port; low power mode.

Internal PLL generates up to 266 MHz clock for the SC1400 core

and up to 133 MHz for the crossbar switch, DMA channels, M2

memory, and other peripherals.

Clock synthesis module provides predivision of PLL input clock;

independent clocking of the internal timers and DDR module;

programmable operation in the SC1400 low power Stop mode;

independent shutdown of different regions of the device.

Enhanced 16-bit wide host interface (HDI16) provides a glueless

connection to industry-standard microcomputers,

microprocessors, and DSPs and can also operate with an 8-bit host

data bus, making if fully compatible with the DSP56300 HI08

from the external host side.

DDR memory controller that supports byte enables for up to a

32-bit data bus; glueless interface to 133 MHz 14-bit page mode

DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;

and 16-bit or 32-bit external data bus.

•

Programmable memory interface with independent read buffers,

programmable predictive read feature for each buffer, and a write

buffer.

System control unit performs software watchdog timer function;

includes programmable bus time-out monitors on AHB-Lite slave

buses; includes bus error detection and programmable time-out

monitors on AHB-Lite master buses; and has address

out-of-range detection on each crossbar switch buses.

Event port collects and counts important signal events including

DMA and interrupt requests and trigger events such as interrupts,

breakpoints, DMA transfers, or wake-up events; units operate

independently, in sequence, or triggered externally; can be used

standalone or with the OCE10.

•

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与MSC7115VF1000相关器件

型号	品牌	描述	获取价格	数据表
MSC7115VF800	NXP	32-BIT, 200 MHz, OTHER DSP, PBGA400, 17 X 17 MM, BGA-400	获取价格
MSC7115VM1000	NXP	32-BIT, 266 MHz, OTHER DSP, PBGA400, 17 X 17 MM, LEAD FREE, BGA-400	获取价格
MSC7115VM800	NXP	32-BIT, 200MHz, OTHER DSP, PBGA400, 17 X 17 MM, LEAD FREE, BGA-400	获取价格
MSC7116	FREESCALE	Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC	获取价格
MSC7116_08	FREESCALE	Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC	获取价格
MSC7116VF1000	FREESCALE	Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC	获取价格

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