Datasheet > MSC7116VF800

MSC7116VF800

更新时间： 2024-01-17 12:26:22

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
100页	1804K
描述
IC,DSP,16-BIT,CMOS,BGA,400PIN,PLASTIC

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MSC7116VF800 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	Reach Compliance Code：	not_compliant
风险等级：	5.8	Base Number Matches：	1

MSC7116VF800 数据手册

MSC7116

Rev. 8, 12/2005

Freescale Semiconductor

Technical Data

MSC7116

Low-Cost DSP with DDR Controller and 10/100 Mbps Ethernet MAC

128

The MSC7116 device targets

high-bandwidth highly

computational DSP

M2 SRAM

(192 KB)

DMA

ASM2

128

AMDMA

JTAG Port

128

(32 ch)

JTAG

Boot ROM

(8 KB)

to IPBus

applications and is optimized

for Enterprise class packet

telephony applications,

providing a competitive price

per channel for voice over

packet systems.

ASEMI

External Bus

External

Memory

Interface

DSP

Extended

Core

from

IPBus

SC1400

Core

Trace

Buffer

(8 KB)

Host

HDI16

Port

Interface

(HDI16)

ASTH

TDM

Fetch

Unit

2 TDMs

ASAPB

RS-232

GPIO

Instruction

Cache

UART

GPIO

AMIC

APB

(16 KB)

What’s New?

Rev. 8 includes the following

changes:

128

AMEC

Extended

Core

Watchdog

Interface

•

All chapters were updated to

reflect the addition of mask set

1M88B. This change includes

signal descriptions, timing

specifications, pin-outs, and

power computations. Review

all chapters for changes.

Interrupts

PLL/Clock

Interrupt

Control

ASAPB

SRAM

(192 KB)

PLL/Clock

ASM1

ASSB

128

System Control

to/from OCE

64 64

AMENT

P XAXB

Events

Event Port

to EMI

to DMA

Timers

I²C

to Crossbar

Ethernet

MAC

I²C

Note: The arrows show the

direction of the transfer.

IPBus

MII/RMII

Figure 1. MSC7116 Block Diagram

The MSC7116 device is a highly integrated DSP processor that contains the StarCore™ SC1400 core, 384 KB of SRAM

memory, 16 KB 16-way instruction cache, 8 KB boot ROM, two 128-channel time-division multiplexing (TDM) interfaces

with hardware support for µ/A-law decoding/encoding, a UART, a 32-channel DMA controller, a 16-bit host interface

(HDI16) to support an external host processor, a 10/100Base-T MII/RMII, a programmable interrupt controller (PIC), an I²C

interface, two 16-bit quad cascadable timers, GPIO signals, and an on-chip emulator (OCE) and an event port for enhanced

debug and system integration capability. The SC1400 core has four ALUs and performs at 1000 DSP million multiply-

accumulates per second (MMACS) with an internal 266 MHz clock at 1.2 V.

12 3 4 5 6 7...100

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