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MSC7110 PDF预览

MSC7110

更新时间: 2024-01-28 16:29:00
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 双倍数据速率控制器
页数 文件大小 规格书
8页 148K
描述
Low-Cost 16-Bit DSP with DDR Controller

MSC7110 数据手册

 浏览型号MSC7110的Datasheet PDF文件第2页浏览型号MSC7110的Datasheet PDF文件第3页浏览型号MSC7110的Datasheet PDF文件第4页浏览型号MSC7110的Datasheet PDF文件第5页浏览型号MSC7110的Datasheet PDF文件第6页浏览型号MSC7110的Datasheet PDF文件第7页 
MSC7110PB  
Rev. 2, 12/2005  
Freescale Semiconductor  
Product Brief  
MSC7110  
Low-Cost 16-Bit DSP with DDR Controller  
The MSC7110 device  
targets high-bandwidth  
highly computational  
DSP applications and  
is optimized for  
Enterprise class packet  
telephony applications,  
providing a competitive  
price per channel for  
voice over packet  
DMA  
ASM2  
AMDMA  
JTAG Port  
128  
(32 ch)  
Boot ROM  
(8 KB)  
JTAG  
64  
to IPBus  
ASEMI  
External Bus  
External  
DSP  
Extended  
Core  
Memory  
Interface  
from  
IPBus  
64  
32  
SC1400  
Core  
Trace  
Buffer  
(8 KB)  
Host  
HDI16  
Port  
Interface  
(HDI16)  
ASTH  
32  
TDM  
64  
Fetch  
Unit  
TDM  
systems.  
ASAPB  
RS-232  
GPIO  
Instruction  
Cache  
(16 KB)  
UART  
GPIO  
AMIC  
32  
APB  
128  
64  
AMEC  
Extended  
Core  
Interface  
Watchdog  
Interrupts  
PLL/Clock  
Interrupt  
Control  
ASAPB  
32  
M1  
SRAM  
PLL/Clock  
ASM1  
ASSB  
(64 KB)  
128  
64  
64  
System Control  
to/from OCE  
64  
32  
32  
P XA XB  
Events  
Event Port  
to EMI  
to DMA  
Timers  
to Crossbar  
2
I C  
2
I C  
Note: The arrows show the direction of the transfer.  
IPBus  
Figure 1. MSC7110 Block Diagram  
The MSC7110 device is a highly integrated DSP processor that contains the StarCore™ SC1400 core, 64 KB of  
SRAM memory, a 16 KB ICache, an 8 KB boot ROM, a 128-channel time-division multiplexing (TDM) interface  
with hardware support for µ/A-law decoding/encoding, a UART, a 32-channel DMA controller, a 16-bit host  
2
interface (HDI16) to support an external host processor, a programmable interrupt controller (PIC), an I C  
interface, two 16-bit quad cascadable timers, GPIO signals, and an on-chip emulator (OCE) and event port for  
enhanced debug capability. The SC1400 core has four ALUs and performs at 1000 DSP million multiply  
accumulates per second (MMACS) with an internal 266 MHz clock at 1.2 V.  
© Freescale Semiconductor, Inc., 2004, 2005. All rights reserved.  

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