ꢀ ꢁꢂꢃ ꢄ ꢃꢃ ꢅ ꢀ ꢁꢂ ꢃ ꢄꢃ ꢄ
ꢀ ꢁꢂꢃ ꢄ ꢃ ꢆ ꢅ ꢀ ꢁꢂ ꢃ ꢄꢃ ꢇ
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
MSC121xYX FAMILY FEATURES
(1)
(2)
(2)
(2)
(2)
MSC121xY5
FEATURES
MSC121xY2
MSC121xY3
MSC121xY4
Up to 16k
Up to 16k
256
Flash Program Memory (Bytes)
Flash Data Memory (Bytes)
Internal Scratchpad SRAM (Bytes)
Internal MOVX RAM (Bytes)
Externally Accessible Memory (Bytes)
Up to 4k
Up to 4k
256
Up to 8k
Up to 8k
Up to 32k
Up to 32k
256
256
1024
1024
1024
1024
64k Program, 64k Data
64k Program, 64k Data
64k Program, 64k Data
64k Program, 64k Data
(1)
(2)
All peripheral features are the same on all devices; the flash memory size is the only difference.
The last digit of the part number (N) represents the onboard flash size = (2N)kBytes.
ELECTRICAL CHARACTERISTICS: AVDD = 5V
3
All specifications from T
to T
, DV
= +2.7V to 5.25V, AV
= +5V, f
= 15.625kHz, PGA = 1, filter = Sinc , Buffer ON, f
= 10Hz, Bipolar, f
= 8MHz,
= 200pF, unless otherwise noted.
MIN
MAX
DD
DD
MOD
, V
DAC REF
DATA
CLK
and V
REF
≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. For V
= AV , R
DD LOAD
= 10kΩ, and C
LOAD
MSC1211/12/13/14
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
Analog Inputs (AIN0−AIN7, AINCOM)
Buffer OFF
Buffer ON
AGND − 0.1
AV
AV
+ 0.1
V
V
DD
DD
Analog Input Range
AGND + 50mV
− 1.5
/PGA
Full-Scale Input Voltage Range
Differential Input Impedance
Input Current
(AIN+) − (AIN−)
Buffer OFF
Buffer ON
V
V
REF
(1)
7/PGA
MΩ
nA
0.5
Fast Settling Filter
2
−3dB
0.469 • fDATA
0.318 • fDATA
0.262 • fDATA
Sinc Filter
−3dB
Bandwidth
3
Sinc Filter
−3dB
Programmable Gain Amplifier
Input Capacitance
User-Selectable Gain Range
Buffer ON
1
128
9
0.5
2
pF
pA
µA
Input Leakage Current
Burnout Current Sources
Multiplexer Channel ON, T = +25°C
Buffer ON
ADC Offset DAC
Offset DAC Range
Bipolar Mode
V /(2 • PGA)
REF
V
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
8
Bits
1.5
1
% of Range
ppm/°C
System Performance
Resolution
24
Bits
Bits
ENOB
See Typical Characteristics
22
Output Noise
See Typical Characteristics
No Missing Codes
Integral Nonlinearity
Offset Error
Sinc3 Filter, Decimation >360
End Point Fit, Bipolar Mode
After Calibration
24
Bits
%FSR
ppm of FS
ppm of FS/°C
%
3
0.0015
3.5
(2)
Offset Drift
Before Calibration
0.001
−0.002
0.5
(3)
Gain Error
After Calibration
(2)
Gain Error Drift
Before Calibration
ppm/°C
% of FS
% of FS
dB
System Gain Calibration Range
System Offset Calibration Range
80
120
50
−50
At DC
115
130
120
120
100
100
92
f
f
f
f
f
= 60Hz, f
= 50HZ, f
= 60Hz, f
= 10Hz
= 50Hz
= 60Hz
= 50Hz
= 60Hz
dB
CM
CM
CM
SIG
SIG
DATA
DATA
DATA
Common-Mode Rejection
Normal-Mode Rejection
dB
dB
= 50Hz, f
= 60Hz, f
dB
DATA
dB
DATA
(4)
Power-Supply Rejection
(1)
At DC, dB = −20log(∆VOUT/∆V
)
dB
DD
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Calibration can minimize these errors.
The self gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
∆V is change in digital result.
OUT
9pF switched capacitor at fSAMP clock frequency (see Figure 14).
Linearity calculated using a reduced code range of 512 to 65024; output unloaded.
Ensured by design and characterization; not production tested.
Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).
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