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MPXR2005VMM80R PDF预览

MPXR2005VMM80R

更新时间: 2022-02-26 10:40:12
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 微控制器
页数 文件大小 规格书
30页 137K
描述
32-bit Power Architecture® Microcontrollers for Highly Reliable

MPXR2005VMM80R 数据手册

 浏览型号MPXR2005VMM80R的Datasheet PDF文件第23页浏览型号MPXR2005VMM80R的Datasheet PDF文件第24页浏览型号MPXR2005VMM80R的Datasheet PDF文件第25页浏览型号MPXR2005VMM80R的Datasheet PDF文件第27页浏览型号MPXR2005VMM80R的Datasheet PDF文件第28页浏览型号MPXR2005VMM80R的Datasheet PDF文件第29页 
Features  
2.5.39 Built-In Self-Test (BIST) Capability  
This device includes the following protection against latent faults:  
Boot-time Memory Built-In Self-Test (MBIST)  
Boot-time scan-based Logic Built-In Self-Test (LBIST)  
Run-time ADC Built-In Self-Test (BIST)  
Run-time Built-In Self Test of LVDs  
2.5.40 IEEE 1149.1 JTAG Controller (JTAGC)  
The JTAGC block provides the means to test chip functionality and connectivity while remaining  
transparent to system logic when not in test mode. All data input to and output from the JTAGC block is  
communicated in serial format. The JTAGC block is compliant with the IEEE standard.  
The JTAG controller provides the following features:  
IEEE Test Access Port (TAP) interface with 5 pins:  
— TDI  
— TMS  
— TCK  
— TDO  
— JCOMP  
Selectable modes of operation include JTAGC/debug or normal system operation  
5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:  
— BYPASS  
— IDCODE  
— EXTEST  
— SAMPLE  
— SAMPLE/PRELOAD  
3 test data registers: a bypass register, a boundary scan register, and a device identification register.  
The size of the boundary scan register is parameterized to support a variety of boundary scan chain  
lengths.  
TAP controller state machine that controls the operation of the data registers, instruction register  
and associated circuitry  
2.5.41 Nexus Port Controller (NPC)  
The NPC module provides real-time development support capabilities for this device in compliance with  
the IEEE-ISTO 5001-2008 standard. This development support is supplied for MCUs without requiring  
external address and data pins for internal visibility.  
The NPC block interfaces to the host processor and internal buses to provide development support as per  
the IEEE-ISTO 5001-2008 Class 3+, including selected features from Class 4 standard.  
PXS20 Product Brief, Rev. 1  
26  
Freescale Semiconductor  

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