Datasheet > MPXR4030VVU264

MPXR4030VVU264

更新时间： 2022-04-07 12:00:17

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		微控制器
页数	文件大小	规格书
23页	116K
描述
32-bit Power ArchitectureÂ® Microcontrollers for Real-Time Applications

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MPXR4030VVU264 数据手册

Freescale Semiconductor

Product Brief

Document Number: PXR40PB

Rev. 1, 06/2011

PXR40 Product Brief

32-bit Power Architecture^®Microcontrollers for Real-Time

Applications

Contents

The PXR40 series 32-bit microcontrollers provide

integrated analog and processing power to give industrial

Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 PXR40 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.2 PXR40 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 4

2.3 Critical Performance Parameters. . . . . . . . . . . . . . . 6

2.4 Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.5 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Developer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Orderable Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

users a reliable, robust controller solution to meet a

variety of timing critical application needs, such as

motion/motor control, without sacrificing performance

during complex operations. Based on Power

Architecture , these system-on-chip devices are 100%

user-mode compatible with the classic Power

Architecture instruction set.

The e200z7 host processor core of the PXR40 is

compatible with the Power Architecture Book E

architecture. It is 100% user-mode compatible (with

floating point library) with the classic PowerPC

instruction set. The Book E architecture has

enhancements that improve the architecture’s fit in

embedded applications. In addition to the classic

PowerPC instruction set, this core also has additional

instruction support for digital signal processing (DSP).

The PXR40 has two levels of memory hierarchy, a

16 KB instruction + 16 KB data cache in a Harvard

Preliminary—Subject to Change Without Notice

12 3 4 5 6 7...23

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