Datasheet > MPC862PCVR80B

MPC862PCVR80B

更新时间： 2024-01-26 12:25:22

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
88页	1299K
描述
RISC PROCESSOR

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数据手册

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MPC862PCVR80B 数据手册

Features

•

System integration unit (SIU)

— Bus monitor

— Software watchdog

— Periodic interrupt timer (PIT)

— Low-power stop mode

— Clock synthesizer

— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture

— Reset controller

— IEEE 1149.1 test access port (JTAG)

Interrupts

•

— Seven external interrupt request (IRQ) lines

— 12 port pins with interrupt capability

— The MPC862P and MPC862T have 23 internal interrupt sources; the MPC857T and

MPC857DSL have 20 internal interrupt sources

— Programmable priority between SCCs (MPC862P and MPC862T)

— Programmable highest priority request

Communications processor module (CPM)

— RISC controller

— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT

MODE, and RESTART TRANSMIT)

— Supports continuous mode transmission and reception on all serial channels

— Up to 8-Kbytes of dual-port RAM

— The MPC862P and MPC862T have 16 serial DMA (SDMA) channels; the MPC857T and

MPC857DSL have 10 serial DMA (SDMA) channels

— Three parallel I/O registers with open-drain capability

Four baud rate generators

•

— Independent (can be connected to any SCC or SMC)

— Allow changes during operation

— Autobaud support option

The MPC862P and MPC862T have four SCCs (serial communication controller) The MPC857T

and MPC857DSL have one SCC, SCC1; the MPC857DSL supports ethernet only

— Serial ATM capability on all SCCs

— Optional UTOPIA port on SCC4

— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation

— HDLC/SDLC

— HDLC bus (implements an HDLC-based local area network (LAN))

— Asynchronous HDLC to support PPP (point-to-point protocol)

— AppleTalk

MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3

Freescale Semiconductor

1 2 345 6 7...88

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