MPC860T Architecture Overview
in the processor except the minimum logic required to restart the device, providing the lowest power
consumption but requiring the longest wake-up time.
1.2.3.3 Communications Processor Module (CPM)
The MPC860 PowerQUICC family, like the earlier generation MC68360 QUICC, implements a dual-
processor architecture. This dual-processor architecture provides both a high-performance, general-purpose
processor for application programming use as well as a special-purpose communications processor module
(CPM) uniquely designed for communications needs.
The CPM contains features that allow the PowerQUICC to excel in communications and networking
products. These features may be divided into three subgroups:
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Communications processor (CP)
Sixteen independent serial DMA (SDMA) controllers
Four general-purpose timers
The CP provides the communication features of the MPC860 PowerQUICC family. Included are a RISC
processor, four serial communication controllers (SCC), two serial management controllers (SMC), one
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serial peripheral interface (SPI), one I C Interface, 5 Kbytes of dual-port RAM, an interrupt controller, a
time slot assigner, three parallel ports, a parallel interface port, four independent baud rate generators, and
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sixteen serial DMA channels to support the SCCs, SMCs, SPI, and I C.
The SDMAs provide two channels of general-purpose DMA capability for each communications channel.
They offer high-speed transfers, 32-bit data movement, buffer chaining, and independent request and
acknowledge logic.
The four general-purpose timers on the CPM are identical to the timers found on the MC68360 and still
support the internal cascading of two timers to form a 32-bit timer.
The PowerQUICC family maintains the best features of the MC68360 QUICC, while making changes
required to provide for the increased flexibility, integration, and performance requested by customers
demanding the performance of the PowerPC architecture. Because the CPM architectural approach remains
intact between the PowerQUICC family and the MC68360 QUICC, a user of the MC68360 QUICC can
easily become familiar with the PowerQUICC.
Additionally, like the MC68MH360, QUICC32, and the MPC860MH, the MPC860T supports the QMC
microcode, enabling it to provide protocol processing for multiple time-division-multiplexed channels over
a single SCC.
1.2.3.4 The QMC Microcode
The standard MPC860 can handle one logical channel performing the protocol framework for each of its
serial channels. This logical channel is used in time-division-multiplexed interfaces. In contrast, the QMC
microcode emulates up to 64 serial controllers that can operate in either HDLC mode or transparent mode
within one single SCC.
Refer to the QMC Supplement to MC68360 and MPC860 User’s Manuals for more details about the
features and operation of the QMC microcode.
1.2.4 Software Compatibility Issues
The following list summarizes the major software differences between the MC68360 QUICC and the
MOTOROLA
MPC860TPowerQUICC™TechnicalSummary
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