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MPC8572EPXAVNE

更新时间: 2024-11-08 14:59:31
品牌 Logo 应用领域
恩智浦 - NXP PC双倍数据速率
页数 文件大小 规格书
141页 1507K
描述
PowerQUICC 32-Bit Power Arch SoC, 2 X 1.5GHz, DDR2/3, PCIe, GbE, SRIO, SEC, 0 to 105C, R2.2.1

MPC8572EPXAVNE 数据手册

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NXP Semiconductors  
Technical Data  
Document Number: MPC8572EEC  
Rev. 7, 03/2016  
MPC8572E PowerQUICC III  
Integrated Processor  
Hardware Specifications  
Contents  
1 Overview  
This section provides a high-level overview of the features  
of the MPC8572E processor. Figure 1 shows the major  
functional units within the MPC8572E.  
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10  
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15  
4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18  
6. DDR2 and DDR3 SDRAM Controller . . . . . . . . . . . 19  
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
8. Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 28  
9. Ethernet Management Interface  
1.1  
Key Features  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 50  
10. Local Bus Controller (eLBC) . . . . . . . . . . . . . . . . . . 53  
11. Programmable Interrupt Controller . . . . . . . . . . . . . 65  
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65  
13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67  
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70  
15. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 72  
16. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83  
17. Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91  
18. Package Description . . . . . . . . . . . . . . . . . . . . . . . . 101  
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120  
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125  
21. System Design Information . . . . . . . . . . . . . . . . . . 127  
22. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 137  
23. Document Revision History . . . . . . . . . . . . . . . . . . 139  
The following list provides an overview of the MPC8572E  
feature set:  
Two high-performance, 32-bit, Book E-enhanced  
cores that implement the Power Architecture®  
technology:  
— Each core is identical to the core within the  
MPC8572E processor.  
— 32-Kbyte L1 instruction cache and 32-Kbyte L1  
data cache with parity protection. Caches can be  
locked entirely or on a per-line basis, with  
separate locking for instructions and data.  
— Signal-processing engine (SPE) APU (auxiliary  
processing unit). Provides an extensive  
instruction set for vector (64-bit) integer and  
fractional operations. These instructions use both  
NXP reserves the right to change the detail specifications as may be required to permit improvements in  
the design of its products.  
¬© 2008-2011, 2014, 2016 NXP B.V.  
 

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