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MPC8535AVTAQGA PDF预览

MPC8535AVTAQGA

更新时间： 2024-11-06 15:44:07
品牌 Logo 应用领域
恩智浦 - NXP 时钟外围集成电路
页数 文件大小 规格书
126页 1439K
描述
32-BIT, 1000MHz, MICROPROCESSOR, PBGA783, 29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, FCPBGA-783

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MPC8535AVTAQGA 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, FCPBGA-783
针数：783Reach Compliance Code：not_compliant
ECCN代码：5A992HTS代码：8542.31.00.01
风险等级：5.44地址总线宽度：32
位大小：32边界扫描：YES
最大时钟频率：133 MHz外部数据总线宽度：32
格式：FLOATING POINT集成缓存：YES
JESD-30 代码：S-PBGA-B783JESD-609代码：e2
长度：29 mm低功率模式：YES
湿度敏感等级：3端子数量：783
最高工作温度：90 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA783,28X28,40封装形状：SQUARE
封装形式：GRID ARRAY电源：1,1.5/1.8,1.8/3.3 V
认证状态：Not Qualified座面最大高度：2.76 mm
速度：1000 MHz子类别：Microprocessors
最大供电电压：1.05 V最小供电电压：0.95 V
标称供电电压：1 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：Tin/Silver (Sn/Ag)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
宽度：29 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR
Base Number Matches：1

MPC8535AVTAQGA 数据手册

 浏览型号MPC8535AVTAQGA的Datasheet PDF文件第2页浏览型号MPC8535AVTAQGA的Datasheet PDF文件第3页浏览型号MPC8535AVTAQGA的Datasheet PDF文件第4页浏览型号MPC8535AVTAQGA的Datasheet PDF文件第5页浏览型号MPC8535AVTAQGA的Datasheet PDF文件第6页浏览型号MPC8535AVTAQGA的Datasheet PDF文件第7页 
Freescale Semiconductor  
Data Sheet: Technical Data  
Document Number: MPC8535EEC  
Rev. 5, 09/2011  
MPC8535E  
MPC8535E PowerQUICC III  
Integrated Processor  
Hardware Specifications  
MAPBGA–783  
29 mm x 29 mm  
• High-performance, 32-bit e500 core, scaling up to  
1.25 GHz, that implements the Power Architecture®  
technology  
– Support for various Ethernet physical interfaces: GMII,  
TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII  
– Support TCP/IP acceleration and QOS features  
– MAC address recognition and RMON statistics support  
– Support ARP parsing and generating wake-up events  
based on the parsing results while in deep sleep mode  
– Support accepting and storing packets while in deep  
sleep mode  
– 36-bit physical addressing  
– Double-precision embedded floating point APU using  
64-bit operands  
– Embedded vector and scalar single-precision  
floating-point APUs using 32- or 64-bit operands  
– Memory management unit (MMU)  
• High-speed interfaces (multiplexed) supporting:  
– Two PCI Express interfaces  
• Integrated L1/L2 cache  
– L1 cache—32-Kbyte data and 32-Kbyte instruction  
– L2 cache—512-Kbyte (8-way set associative)  
• DDR2/DDR3 SDRAM memory controller with full ECC  
support  
– PCI Express 1.0a compatible  
– One x4/x2/x1 PCI Express interface  
–
Two x2/x1 ports  
– One SGMII interface  
– One Serial ATA (SATA) controller supports SATA I and  
SATA I data rates  
– One 64-bit/32-bit data bus  
– Up to 250-MHz clock (500-MHz data rate)  
– Supporting up to 16 Gbytes of main memory  
– Using ECC, detects and corrects all single-bit errors and  
detects all double-bit errors and all errors within a nibble  
– Invoke a level of system power management by  
asserting MCKE SDRAM signal on-the-fly to put the  
memory into a low-power sleep mode  
• PCI 2.2 compatible PCI controller  
• Two universal serial bus (USB) dual-role controllers  
comply with USB specification revision 2.0  
• 133-MHz, 32-bit, enhanced local bus (eLBC) with memory  
controller  
• Enhanced secured digital host controller (eSDHC) used for  
SD/MMC card interface  
– Both hardware and software options to support  
battery-backed main memory  
– Support boot capability from eSDHC  
• Integrated four-channel DMA controller  
• Integrated security engine (SEC) optimized to process all  
the algorithms associated with IPsec, IKE, SSL/TLS,  
iSCSI, SRTP, IEEE Std 802.16e™, and 3GPP.  
– XOR engine for parity checking in RAID storage  
applications  
2
• Dual I C and dual universal asynchronous  
receiver/transmitter (DUART) support  
• Programmable interrupt controller (PIC)  
• Power management, low standby power  
• Enhanced Serial peripheral interfaces (eSPI)  
– Support boot capability from eSPI  
• Two enhanced three-speed Ethernet controllers (eTSECs)  
with SGMII support  
– Support Doze, Nap, Sleep, Jog, and Deep Sleep mode  
– PMC wake on: LAN activity, USB connection or remote  
wakeup, GPIO, internal timer, or external interrupt event  
• System performance monitor  
– Three-speed support (10/100/1000 Mbps)  
– Two IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x,  
IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and  
IEEE Std 1588™-compatible controllers  
• IEEE Std 1149.1™-compatible, JTAG boundary scan  
• 783-pin FC-PBGA package, 29 mm × 29 mm  
© 2011 Freescale Semiconductor, Inc. All rights reserved.  
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