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MPC5606BCLU4R PDF预览

MPC5606BCLU4R

更新时间： 2024-11-10 04:48:23
品牌 Logo 应用领域
恩智浦 - NXP 微控制器
页数 文件大小 规格书
110页 907K
描述
IC,MICROCONTROLLER,32-BIT,CMOS,QFP,176PIN,PLASTIC

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中文翻译

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MPC5606BCLU4R 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：QFP包装说明：QFP, QFP176,1.0SQ,20
针数：176Reach Compliance Code：compliant
风险等级：5.8位大小：32
JESD-30 代码：S-PQFP-G176端子数量：176
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP176,1.0SQ,20封装形状：SQUARE
封装形式：FLATPACK电源：3.3/5 V
认证状态：Not QualifiedRAM（字节）：81920
ROM（单词）：1048576ROM可编程性：FLASH
速度：48 MHz子类别：Microcontrollers
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
Base Number Matches：1

MPC5606BCLU4R 数据手册

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Freescale Semiconductor  
Data Sheet: Technical Data  
Document Number: MPC5607B  
Rev. 6, 07/2011  
MPC5607B  
144 LQFP  
100 LQFP  
20 mm x 20 mm  
14 mm x 14 mm  
176 LQFP  
24 mm x 24 mm  
208 MAPBGA  
17 mm x 17 mm  
MPC5607B Microcontroller  
Data Sheet  
• Single issue, 32-bit CPU core complex (e200z0h)  
• Up to 149 configurable general purpose pins supporting  
input and output operations (package dependent)  
• Real-Time Counter (RTC)  
®
– Compliant with the Power Architecture technology  
embedded category  
– Enhanced instruction set allowing variable length  
encoding (VLE) for code size footprint reduction. With  
the optional encoding of mixed 16-bit and 32-bit  
instructions, it is possible to achieve significant code  
size footprint reduction.  
– Clock source from internal 128 kHz or 16 MHz  
oscillator supporting autonomous wakeup with 1 ms  
resolution with maximum timeout of 2 seconds  
– Optional support for RTC with clock source from  
external 32 kHz crystal oscillator, supporting wakeup  
with 1 sec resolution and maximum timeout of 1 hour  
• Up to 8 periodic interrupt timers (PIT) with 32-bit counter  
resolution  
• Nexus development interface (NDI) per IEEE-ISTO  
5001-2003 Class Two Plus  
• Device/board boundary scan testing supported per Joint  
Test Action Group (JTAG) of IEEE (IEEE 1149.1)  
• On-chip voltage regulator (VREG) for regulation of input  
supply for all internal levels  
• Up to 1.5 MB on-chip code flash memory supported with  
the flash memory controller  
• 64 (4 × 16) KB on-chip data flash memory with ECC  
• Up to 96 KB on-chip SRAM  
• Memory protection unit (MPU) with 8 region descriptors  
and 32-byte region granularity on certain family members  
(Refer to Table 1 for details.)  
• Interrupt controller (INTC) capable of handling 204  
selectable-priority interrupt sources  
• Frequency modulated phase-locked loop (FMPLL)  
• Crossbar switch architecture for concurrent access to  
peripherals, Flash, or RAM from multiple bus masters  
• 16-channel eDMA controller with multiple transfer request  
sources using DMA multiplexer  
• Boot assist module (BAM) supports internal Flash  
programming via a serial link (CAN or SCI)  
• Timer supports I/O channels providing a range of 16-bit  
input capture, output compare, and pulse width modulation  
functions (eMIOS)  
• 2 analog-to-digital converters (ADC): one 10-bit and one  
12-bit  
• Cross Trigger Unit to enable synchronization of ADC  
conversions with a timer event from the eMIOS or PIT  
• Up to 6 serial peripheral interface (DSPI) modules  
• Up to 10 serial communication interface (LINFlex)  
modules  
• Up to 6 enhanced full CAN (FlexCAN) modules with  
configurable buffers  
2
• 1 inter-integrated circuit (I C) interface module  
© Freescale Semiconductor, Inc., 2010-2011. All rights reserved.  
1234567...110

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