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MPC5602F0VLL6R PDF预览

MPC5602F0VLL6R

更新时间: 2024-01-05 08:45:02
品牌 Logo 应用领域
恩智浦 - NXP 控制器微控制器微控制器和处理器
页数 文件大小 规格书
95页 1689K
描述
32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP100, 14 X 14 MM, 1.40 MM, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-100

MPC5602F0VLL6R 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:unknownECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:5.66
Is Samacsys:N具有ADC:YES
其他特性:ALSO OPERATES AT MIN 3V地址总线宽度:
位大小:32最大时钟频率:40 MHz
DAC 通道:NODMA 通道:YES
外部数据总线宽度:JESD-30 代码:S-PQFP-G100
长度:14 mmI/O 线路数量:72
端子数量:100最高工作温度:125 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
认证状态:Not QualifiedROM可编程性:FLASH
座面最大高度:1.7 mm速度:64 MHz
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLER, RISCBase Number Matches:1

MPC5602F0VLL6R 数据手册

 浏览型号MPC5602F0VLL6R的Datasheet PDF文件第3页浏览型号MPC5602F0VLL6R的Datasheet PDF文件第4页浏览型号MPC5602F0VLL6R的Datasheet PDF文件第5页浏览型号MPC5602F0VLL6R的Datasheet PDF文件第7页浏览型号MPC5602F0VLL6R的Datasheet PDF文件第8页浏览型号MPC5602F0VLL6R的Datasheet PDF文件第9页 
Table 2. MPC5602P series block summary  
Function  
Block  
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter  
Boot assist module (BAM)  
Block of read-only memory containing VLE code which is executed according to  
the boot mode of the device  
Clock generation module  
(MC_CGM)  
Provides logic and control required for the generation of system and peripheral  
clocks  
Controller area network (FlexCAN) Supports the standard CAN communications protocol  
Cross triggering unit (CTU)  
Enables synchronization of ADC conversions with a timer event from the eMIOS  
or from the PIT  
Crossbar switch (XBAR)  
Supports simultaneous connections between two master ports and three slave  
ports; supports a 32-bit address bus width and a 32-bit data bus width  
Cyclic redundancy check (CRC) CRC checksum generator  
Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices  
(DSPI)  
Enhanced direct memory access Performs complex data transfers with minimal intervention from a host processor  
(eDMA)  
via “n” programmable channels  
Enhanced timer (eTimer)  
Provides enhanced programmable up/down modulo counting  
Error correction status module  
(ECSM)  
Provides a myriad of miscellaneous control functions for the device including  
program-visible information about configuration and revision levels, a reset  
status register, wakeup control for exiting sleep modes, and optional features  
such as information on memory errors reported by error-correcting codes  
External oscillator (XOSC)  
Provides an output clock used as input reference for FMPLL_0 or as reference  
clock for specific modules depending on system needs  
Fault collection unit (FCU)  
Flash memory  
Provides functional safety to the device  
Provides non-volatile storage for program code, constants and variables  
Frequency-modulated  
phase-locked loop (FMPLL)  
Generates high-speed system clocks and supports programmable frequency  
modulation  
Interrupt controller (INTC)  
JTAG controller  
Provides priority-based preemptive scheduling of interrupt requests  
Provides the means to test chip functionality and connectivity while remaining  
transparent to system logic when not in test mode  
LINFlex controller  
Manages a high number of LIN (Local Interconnect Network protocol) messages  
efficiently with a minimum of CPU load  
Mode entry module (MC_ME)  
Provides a mechanism for controlling the device operational mode and mode  
transition sequences in all functional states; also manages the power control unit,  
reset generation module and clock generation module, and holds the  
configuration, control and status registers accessible for applications  
Periodic interrupt timer (PIT)  
Peripheral bridge (PBRIDGE)  
Power control unit (MC_PCU)  
Produces periodic interrupts and triggers  
Is the interface between the system bus and on-chip peripherals  
Reduces the overall power consumption by disconnecting parts of the device  
from the power supply via a power switching device; device components are  
grouped into sections called “power domains” which are controlled by the PCU  
MPC5602P Microcontroller Data Sheet, Rev. 4.1  
6
Freescale Semiconductor  

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