Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5602P
Rev. 6,12/2012
MPC5602P
MPC5602P Microcontroller
Data Sheet
100 LQFP (14 mm x 14 mm)
64 LQFP (10 mm x 10 mm)
•
Up to 64 MHz, single issue, 32-bit CPU core complex
(e200z0h)
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1 FlexCAN interface (2.0B Active) with 32 message
buffers
1 safety port based on FlexCAN with 32 message
buffers and up to 8 Mbit/s at 64 MHz capabilitym
usable as second CAN when not used as safety port
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Compliant with Power Architecture embedded
category
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Variable Length Encoding (VLE)
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One 10-bit analog-to-digital converter (ADC)
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Memory organization
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Up to 16 input channels (16 ch on 100 LQFP and
12 ch on 64 LQFP)
Conversion time < 1 µs including sampling time at
full precision
Programmable Cross Triggering Unit (CTU)
4 analog watchdogs with interrupt capability
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Up to 256 KB on-chip code flash memory with ECC
and erase/program controller
Optional: additional 64 (4 × 16) KB on-chip data
flash memory with ECC for EEPROM emulation
Up to 20 KB on-chip SRAM with ECC
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Fail-safe protection
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On-chip CAN/UART bootstrap loader with Boot Assist
Module (BAM)
1 FlexPWM unit
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Programmable watchdog timer
Non-maskable interrupt
Fault collection unit
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8 complementary or independent outputs with ADC
synchronization signals
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Nexus Class 1 interface
Interrupts and events
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Polarity control, reload unit
Integrated configurable dead time unit and inverter
fault input pins
16-bit resolution
Lockable configuration
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16-channel eDMA controller
16 priority level controller
Up to 25 external interrupts
PIT implements four 32-bit timers
120 interrupts are routed via INTC
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Clock generation
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General purpose I/Os
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4–40 MHz main oscillator
Individually programmable as input, output or special
function
37 on 64 LQFP
64 on 100 LQFP
16 MHz internal RC oscillator
Software-controlled FMPLL capable of up to
64 MHz
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Voltage supply
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1 general purpose eTimer unit
3.3 V or 5 V supply for I/Os and ADC
On-chip single supply voltage regulator with external
ballast transistor
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6 timers each with up/down capabilities
16-bit resolution, cascadeable counters
Quadrature decode with rotation direction flag
Double buffer input capture and output compare
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Operating temperature ranges: –40 to 125 °C or –40
to 105 °C
Communications interfaces
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Up to 2 LINFlex modules (1× Master/Slave, 1×
Master only)
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Up to 3 DSPI channels with automatic chip select
generation (up to 8/4/4 chip selects)
This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
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