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MN3890S

更新时间： 2024-11-11 10:51:03
品牌 Logo 应用领域
松下 - PANASONIC /
页数 文件大小 规格书
6页 55K
描述
NTSC-Compatible CCD 1 H Video Signal Delay Element

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中文翻译

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MN3890S 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP8,.25
针数：8Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.92
商用集成电路类型：CONSUMER CIRCUITJESD-30 代码：R-PDSO-G8
JESD-609代码：e0长度：5 mm
功能数量：1端子数量：8
最高工作温度：60 °C最低工作温度：-20 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE电源：5 V
认证状态：Not Qualified座面最大高度：1.9 mm
子类别：Other Consumer ICs最大压摆率：46 mA
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：4.2 mm
Base Number Matches：1

MN3890S 数据手册

 浏览型号MN3890S的Datasheet PDF文件第2页浏览型号MN3890S的Datasheet PDF文件第3页浏览型号MN3890S的Datasheet PDF文件第4页浏览型号MN3890S的Datasheet PDF文件第5页浏览型号MN3890S的Datasheet PDF文件第6页 
CCD Delay Line Series  
MN3890S  
NTSC-Compatible CCD 1 H Video Signal Delay Element  
Overview  
Pin Assignment  
The MN3890S is a 1 H image delay element of a 4 fSC  
CMOS CCD and suitable for video signal processing ap-  
plications.  
VIN  
VBB  
VDD  
VSS  
1
2
3
4
8
7
6
5
VO  
It contains such components as a frequency-doubler  
circuit, a shift register clock driver, a 906-stage CCD ana-  
log shift register, and a resampling output amplifier.  
The MN3885S drives and samples the 906-stage ana-  
log shift register using a redoubled version of the sup-  
plied clock signal with a frequency 7.16 MHz of twice  
the NTSC color signal subcarrier frequency, and after add-  
ing in the attached filter delay, produces a delay of 1 H  
(the horizontal scan period).  
VGC  
PCOUT  
&
VCOIN  
XI  
( TOP VIEW )  
SOP008-P-0225A  
Features  
Single 5.0 V power supply  
Energy-saving design based on CMOS process  
Low EMI levels from clock during driving  
Applications  
VCRs, Video cameras  
Structure and Operation  
The MN3890S consists of the operational blocks shown  
in the block diagram.  
The shift register samples the shift register input with  
the sampling clock øS, and converts the results to charges,  
and uses transfer clocks ø1 and ø2 to transfer the results  
to the following block, the charge detection block, where  
the charges is converted into a voltage signal.  
Frequency-doubler circuit  
When the 7.16 MHz of the doubled NTSC color signal  
subcarrier frequency is inputted from the clock input pin  
XI, 14.32 MHz clock of fourfold frequency of color sig-  
nal subcarrier is generated by this circuit.  
Resampling output amplifier  
In the output amplifier, this voltage signal is done  
Sample-and-Hold by resampling, and Y-signal as it is  
outputted at Vo.  
Clock driver  
Operation  
This block generates two transfer clock signals, ø1 and  
ø2, synchronized with the 14.32 MHz clock signal from  
the frequency-doubler circuit.  
The following is an explanation of delay line opera-  
tion.  
It also generates the sampling clock signals øS and øS',  
resampling clock signal øSH, and reset clock signal øR  
that have adjusted timing relations with ø1 and ø2.  
The waveforms driving the shift registers are as shown  
in the timing chart on page 622.  
The input signal voltage sampled during the interval  
between t=0 and t=τc (where τc is one-half the sampling  
interval) appears at the VO output pin at the point  
t=1813τc.  
CCD analog shift register  
This block first converts the analog signal from the VIN  
input signal pin into a voltage signal, and inputs it into  
906-stage analog shift register.  
1
123456

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