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MMCP-67206FV-30 PDF预览

MMCP-67206FV-30

更新时间: 2024-11-30 04:43:47
品牌 Logo 应用领域
TEMIC 先进先出芯片
页数 文件大小 规格书
16页 89K
描述
FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28

MMCP-67206FV-30 数据手册

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M67206F  
16 K 9 High Speed CMOS Parallel FIFO Rad Tolerant  
Introduction  
The M67206F implements a first-in first-out algorithm, Using an array of eight transistors (8 T) memory cell, the  
featuring asynchronous read/write operations. The FULL M67206F combine an extremely low standby supply  
and EMPTY flags prevent data overflow and underflow. current (typ = 0.1 µA) with a fast access time at 15 ns  
The Expansion logic allows unlimited expansion in word over the full temperature range. All versions offer battery  
size and depth with no timing penalties. Twin address backup data retention capability with a typical power  
pointers automatically generate internal read and write consumption at less than 2 µW.  
addresses, and no external address information are  
The M67206F is processed according to the methods of  
required for the Atmel Wireless & Microcontrollers  
the latest revision of the MIL STD 883 (class B or S), ESA  
FIFOs. Address pointers are automatically incremented  
SCC 9000 or QML.  
with the write pin and read pin. The 9 bits wide data are  
used in data communications applications where a parity  
bit for error checking is necessary. The Retransmit pin  
reset the Read pointer to zero without affecting the write  
pointer. This is very useful for retransmitting data when  
an error is detected in the system.  
Features  
D First-in first-out dual port memory  
D 16384 × 9 organisation  
D Fully expandable by word width or depth  
D Asynchronous read/write operations  
D Empty, full and half flags in single device mode  
D Retransmit capability  
D Fast Flag and access times: 15, 30 ns  
D Wide temperature range : – 55 °C to + 125 °C  
D Bi-directional applications  
D Battery back-up operation : 2 V data retention  
D TTL compatible  
D Single 5 V ± 10 % power supply  
D High Performance SCMOS Technology  
1
Rev. D – June 5, 2000  

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