Datasheet > MM74HCU04_05

MM74HCU04_05

更新时间： 2024-09-27 05:08:27

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
7页	88K
描述
Hex Inverter

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数据手册

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MM74HCU04_05 数据手册

September 1983

Revised January 2005

MM74HCU04

Hex Inverter

General Description

Features

The MM74HCU04 inverters utilize advanced silicon-gate

CMOS technology to achieve operating speeds similar to

LS-TTL gates with the low power consumption of standard

CMOS integrated circuits.

■ Typical propagation delay: 7 ns

■ Fanout of 15 LS-TTL loads

■ Quiescent power consumption: 10 µA maximum at room

temperature

The MM74HCU04 is an unbuffered inverter. It has high

noise immunity and the ability to drive 15 LS-TTL loads.

The 74HCU logic family is functionally as well as pin-out

compatible with the standard 74LS logic family. All inputs

are protected from damage due to static discharge by inter-

nal diode clamps to V_CCand ground.

■ Low input current: 1 µA maximum

Ordering Code:

Package

Order Number

Package Description

Number

MM74HCU04M

M14A

M14D

MTC14

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

MM74HCU04MX_NL

MM74HCU04SJ

MM74HCU04MTC

MM74HCU04N

MM74HCU04N_NL

N14A

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Connection Diagram

Schematic Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

DS005296

www.fairchildsemi.com

12 3 4 5 6 7

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