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MM74HCT573WMX PDF预览

MM74HCT573WMX

更新时间: 2024-11-27 11:12:43
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
11页 302K
描述
八路 D 型锁存

MM74HCT573WMX 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active包装说明:SOIC-20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.46Is Samacsys:N
其他特性:BROADSIDE VERSION OF 373系列:HCT
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8015 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.0072 A
湿度敏感等级:3位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TR峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:38 ns
传播延迟(tpd):44 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

MM74HCT573WMX 数据手册

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DATA SHEET  
www.onsemi.com  
Octal D-Type Latch /  
3-STATE Octal D-Type Flip-Flop  
SOIC20 WB  
CASE 751D05  
MM74HCT573/MM74HCT574  
General Description  
The MM74HCT573 octal Dtype latches and MM74HCT574 octal  
Dtype flipflop advanced silicongate CMOS technology, which  
provides the inherent benefits of low power consumption and wide  
power supply range, but are LSTTL input and output characteristic  
and pinout compatible. The 3STATE outputs are capable of driving  
15 LSTTL loads. All inputs are protected from damage due to static  
TSSOP20, 4.4x6.5  
CASE 948AQ  
discharge by internal diodes to V and ground.  
CC  
When the MM74HCT573 Latch Enable input is HIGH, the  
Q outputs will follow the D inputs. When the Latch Enable goes LOW,  
data at the D inputs will be retained at the outputs until Latch Enable  
returns HIGH again. When a high logic level is applied to the Output  
Control input, all outputs go to a high impedance state, regardless  
of what signals are present at the other inputs and the state of the  
storage elements.  
TSSOP20 WB  
CASE 948E  
MARKING DIAGRAMS  
20  
The MM74HCT574 are positive edge triggered flipflops. Data  
at the D inputs, meeting the setup and hold time requirements, are  
transferred to the Q outputs on positive going transitions of the Clock  
(CK) input. When a high logic level is applied to the Output Control  
(OC) input, all outputs go to a high impedance state, regardless  
of what signals are present at the other inputs and the state of  
the storage elements.  
HCT57xA  
AWLYYWW  
1
SOIC20  
The MM74HCT devices are intended to interface between TTL  
and NMOS components and standard CMOS devices. These parts are  
also plug in replacements for LSTTL devices and can be used  
to reduce power consumption in existing designs.  
20  
HCT  
57xA  
ALYW  
Features  
1
TTL Input Characteristic Compatible  
Typical Propagation Delay: 17 ns  
Low Input Current: 1 mA Maximum  
Low Quiescent Current: 160 mA Maximum  
Compatible with Busoriented Systems  
Output Drive Capability: 15 LSTTL Loads  
These are PbFree Devices  
TSSOP20 WB  
HCT57xA = Specific Device Code  
x = 3 or 4  
A
= Assembly Location  
= Wafer Lot  
= Year  
WL, L  
YY, Y  
WW, W  
= Work Week  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 7 of  
this data sheet.  
© Semiconductor Components Industries, LLC, 1990  
1
Publication Order Number:  
December, 2022 Rev. 2  
MM74HCT573/D  

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