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MM74HC42

更新时间： 2024-11-01 23:02:43
品牌 Logo 应用领域
美国国家半导体 - NSC 解码器
页数 文件大小 规格书
4页 143K
描述
BCD-to-Decimal Decoder

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中文翻译

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MM74HC42 数据手册

 浏览型号MM74HC42的Datasheet PDF文件第2页浏览型号MM74HC42的Datasheet PDF文件第3页浏览型号MM74HC42的Datasheet PDF文件第4页 
January 1988  
MM54HC42/MM74HC42  
BCD-to-Decimal Decoder  
General Description  
This decoder utilizes advanced silicon-gate CMOS technol-  
ogy. Data on the four input pins select one of the 10 outputs  
corresponding to the value of the BCD number on the in-  
puts. An output will go low when selected, otherwise it re-  
mains high. If the input data is not a valid BCD number all  
outputs will remain high. The circuit has high noise immunity  
and low power consumption usually associated with CMOS  
circuitry, yet also has speeds comparable to low power  
Schottky TTL (LS-TTL) circuits, and is capable of driving 10  
LS-TTL equivalent loads.  
All inputs are protected from damage due to static dis-  
and ground.  
charge by diodes to V  
CC  
Features  
Y
Typical propagation delay: 15 ns  
Y
Y
Y
Wide supply range: 2V–6V  
Low quiescent current: 80 mA (74HC)  
Fanout of 10 LS-TTL loads  
Connection Diagram  
Truth Table  
Dual-in-line Package  
Inputs  
Outputs  
No.  
D
C
B
A
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
L
L
L
L
L
L
L
L
L
H
L
L
H
H
L
L
H
L
H
L
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
5
6
7
8
9
L
L
L
H
H
H
H
H
L
L
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
INVALID  
TL/F/5301–1  
H
Top View  
e
e
High Level, L Low Level  
H
Order Number MM54HC42 or MM74HC42  
Logic Diagram  
TL/F/5301–2  
C
1995 National Semiconductor Corporation  
TL/F/5301  
RRD-B30M105/Printed in U. S. A.  
1234

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MM74HC423AMX FAIRCHILD

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MM74HC423AN FAIRCHILD

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 		Dual Retriggerable Monostable Multivibrator

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