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MM54HC163

更新时间: 2024-11-25 04:39:35
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美国国家半导体 - NSC 计数器
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6页 148K
描述
Synchronous Decade Counter with Asynchronous Clear

MM54HC163 数据手册

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January 1992  
MM74HC160 Synchronous  
Decade Counter with Asynchronous Clear  
MM54HC161/MM74HC161 Synchronous  
Binary Counter with Asynchronous Clear  
MM54HC162/MM74HC162 Synchronous  
Decade Counter with Synchronous Clear  
MM54HC163/MM74HC163 Synchronous  
Binary Counter with Synchronous Clear  
General Description  
T h e M M 5 4 H C 1 6 0 / M M 7 4 H C 1 6 0 , M M 5 4 H C 1 6 1 /  
M M 7 4 H C 1 6 1 , M M 5 4 H C 1 6 2 / M M 7 4 H C 1 6 2 , a n d  
MM54HC163/MM74HC163 synchronous presettable count-  
ers utilize advanced silicon-gate CMOS technology and in-  
ternal look-ahead carry logic for use in high speed counting  
applications. They offer the high noise immunity and low  
power consumption inherent to CMOS with speeds similar  
to low power Schottky TTL. The ’HC160 and the ’HC162 are  
4 bit decade counters, and the ’HC161 and the ’HC163 are  
4 bit binary counters. All flip-flops are clocked simultaneous-  
ly on the low to high transition (positive edge) of the CLOCK  
input waveform.  
The MM54HC160/MM74HC160 and MM54HC161/  
MM74HC161 counters are cleared asynchronously. When  
the CLEAR is taken low the counter is cleared immediately  
regardless of the CLOCK.  
Two active high enable inputs (ENP and ENT) and a RIP-  
PLE CARRY (RC) output are provided to enable easy cas-  
cading of counters. Both ENABLE inputs must be high to  
count. The ENT input also enables the RC output. When  
enabled, the RC outputs a positive pulse when the counter  
overflows. This pulse is approximately equal in duration to  
the high level portion of the Q output. The RC output is fed  
A
to successive cascaded stages to facilitate easy implemen-  
tation of N-bit counters.  
These counters may be preset using the LOAD input. Pre-  
setting of all four flip-flops is synchronous to the rising edge  
of CLOCK. When LOAD is held low counting is disabled and  
the data on the A, B, C, and D inputs is loaded into the  
counter on the rising edge of CLOCK. If the load input is  
taken high before the positive edge of CLOCK the count  
operation will be unaffected.  
All inputs are protected from damage due to static dis-  
and ground.  
charge by diodes to V  
CC  
Features  
Y
Typical operating frequency: 40 MHz  
Y
Y
Y
Y
Typical propagation delay; clock to Q: 18 ns  
Low quiescent current: 80 mA maximum (74HC Series)  
Low input current: 1 mA maximum  
All of these counters may be cleared by utilizing the CLEAR  
input. The clear function on the MM54HC162/MM74HC162  
and MM54HC163/MM74HC163 counters are synchronous  
to the clock. That is, the counters are cleared on the posi-  
tive edge of CLOCK while the clear input is held low.  
Wide power supply range: 26V  
Connection Diagram  
Truth Tables  
’HC160/HC161  
CLK CLR ENP ENT Load  
Function  
X
X
X
L
X
H
L
L
X
H
X
L
H
L
X
H
X
H
H
H
L
Clear  
H
H
H
H
H
Count & RC disabled  
Count disabled  
Count & RC disabled  
Load  
X
u
H
Increment Counter  
u
e
e
e
low level  
H
X
high level, L  
don’t care,  
e
low to high transition  
u
’HC162/HC163  
CLK CLR ENP ENT Load  
Function  
L
X
H
L
L
X
H
X
L
H
L
X
H
X
H
H
H
L
Clear  
u
X
X
H
H
H
H
H
Count & RC disabled  
Count disabled  
Count & RC disabled  
Load  
TL/F/5008–1  
Order Number MM54HC161/162/163  
or MM74HC160/161/162/163  
X
u
u
H
Increment Counter  
C
1995 National Semiconductor Corporation  
TL/F/5008  
RRD-B30M115/Printed in U. S. A.  

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