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MM54HC164J

更新时间： 2024-11-25 21:07:51
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
4页 114K
描述
HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP14, CERAMIC, DIP-14

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MM54HC164J 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP14,.3Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.17
计数方向：RIGHT系列：HC/UH
JESD-30 代码：R-GDIP-T14JESD-609代码：e0
长度：19.43 mm负载电容（CL）：50 pF
逻辑集成电路类型：SERIAL IN PARALLEL OUT最大频率@ Nom-Sup：3000000 Hz
位数：8功能数量：1
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP14,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：2/6 V
传播延迟（tpd）：254 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Shift Registers
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：7.62 mm
最小 fmax：20 MHzBase Number Matches：1

MM54HC164J 数据手册

 浏览型号MM54HC164J的Datasheet PDF文件第2页浏览型号MM54HC164J的Datasheet PDF文件第3页浏览型号MM54HC164J的Datasheet PDF文件第4页 
January 1988  
MM54HC164/MM74HC164  
8-Bit Serial-in/Parallel-out Shift Register  
General Description  
The MM54HC164/MM74HC164 utilizes advanced silicon-  
gate CMOS technology. It has the high noise immunity and  
low consumption of standard CMOS integrated circuits. It  
also offers speeds comparable to low power Schottky de-  
vices.  
The 54HC/74HC logic family is functionally as well as pin-  
out compatible with the standard 54LS/74LS logic family.  
All inputs are protected from damage due to static dis-  
charge by internal diode clamps to V  
and ground.  
CC  
Features  
Y
This 8-Bit shift register has gated serial inputs and CLEAR.  
Each register bit is a D-type master/slave flip flop. Inputs A  
& B permit complete control over the incoming data. A low  
at either or both inputs inhibits entry of new data and resets  
the first flip flop to the low level at the next clock pulse. A  
high level on one input enables the other input which will  
then determine the state of the first flip flop. Data at the  
serial inputs may be changed while the clock is high or low,  
but only information meeting the setup and hold time re-  
quirements will be entered. Data is serially shifted in and out  
of the 8-Bit register during the positive going transition of  
the clock pulse. Clear is independent of the clock and ac-  
complished by a low level at the CLEAR input.  
Typical operating frequency: 50 MHz  
Y
Y
Y
Y
Typical propagation delay: 19 ns (clock to Q)  
Wide operating supply voltage range: 2–6V  
Low input current: 1 mA maximum  
Low quiescent supply current: 80 mA maximum (74HC  
Series)  
Y
Fanout of 10 LS-TTL loads  
Connection and Logic Diagrams  
Truth Table  
Dual-In-Line Package  
Inputs  
Outputs  
. . .  
Clear  
Clock  
A
B
Q
A
Q
Q
H
B
L
H
H
H
H
X
L
X
X
H
L
X
X
H
X
L
L
L
L
Q
AO  
Q
Q
HO  
BO  
H
L
L
Q
An  
Q
An  
Q
An  
Q
Q
Q
u
u
u
Gn  
Gn  
Gn  
X
e
e
e
Low Level (steady state)  
H
X
High Level (steady state), L  
Irrelevant (any input, including transitions)  
e
Transition from low to high level.  
u
e
the level of Q , Q , or Q , respectively, before the  
A B H  
Q
, Q , Q  
BO  
AO  
HO  
indicated steady state input conditions were established.  
e
the clock; indicated a one-bit shift.  
Q
, Q  
The level of Q or Q before the most recent  
A
transition of  
u
An  
Gn  
G
TL/F/5315–1  
Top View  
Order Number MM54HC164 or MM74HC164  
TL/F/5315–2  
C
1995 National Semiconductor Corporation  
TL/F/5315  
RRD-B30M105/Printed in U. S. A.  
1234

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