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MM54C85 PDF预览

MM54C85

更新时间: 2024-09-26 22:46:11
品牌 Logo 应用领域
美国国家半导体 - NSC 比较器
页数 文件大小 规格书
4页 119K
描述
4-Bit Magnitude Comparator

MM54C85 数据手册

 浏览型号MM54C85的Datasheet PDF文件第2页浏览型号MM54C85的Datasheet PDF文件第3页浏览型号MM54C85的Datasheet PDF文件第4页 
September 1989  
MM54C85/MM74C85 4-Bit Magnitude Comparator  
General Description  
The MM54C85/MM74C85 is a four-bit magnitude compara-  
tor which will perform comparison of straight binary or BCD  
codes. The circuit consists of eight comparing inputs (A0,  
Features  
Y
Wide supply voltage range  
3.0V to 15V  
1.0V  
Y
Guaranteed noise margin  
Y
High noise immunity  
0.4 V (typ.)  
CC  
l
A1, A2, A3, B0, B1, B2, B3), three cascading inputs (A B,  
Y
Low power  
TTL compatibility  
fan out of 2  
driving 74L  
k
e
l
k
B and  
B). This device compares two four-bit words (A and B)  
e
A
A
B and A  
B), and three outputs (A  
B, A  
Y
Expandable to ‘N’ stages  
and determines whether they are ‘‘greater than,’’ ‘‘less  
than,’’ or ‘‘equal to’’ each other by a high level on the appro-  
priate output. For words greater than four-bits, units can be  
Y
Applicable to binary or BCD  
Y
Low power pinout: 54L85/74L85  
l
k
B) of the least significant stage to the cascade inputs  
cascaded by connecting the outputs (A  
B, A  
B, and  
e
l
A
(A  
k
e
B) of the next-significant stage. In  
B, A  
B and A  
addition the least significant stage must have a high level  
voltage (V  
voltage (V  
e
B and A  
) applied to the A  
IN(1)  
B input and low level  
k
l
) applied to A  
IN(0)  
B inputs.  
Logic Diagram  
TL/F/5886–1  
C
1995 National Semiconductor Corporation  
TL/F/5886  
RRD-B30M105/Printed in U. S. A.  

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