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MM54C89

更新时间： 2024-02-09 18:26:12
品牌 Logo 应用领域
美国国家半导体 - NSC 存储
页数 文件大小 规格书
6页 132K
描述
64-Bit TRI-STATE Random Access Read/Write Memory

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中文翻译

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MM54C89 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DFP, FL16,.3Reach Compliance Code：unknown
风险等级：5.92最长访问时间：650 ns
JESD-30 代码：R-XDFP-F16JESD-609代码：e0
内存集成电路类型：STANDARD SRAM内存宽度：4
端子数量：16字数：16 words
字数代码：16工作模式：ASYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：16X4输出特性：3-STATE
封装主体材料：CERAMIC封装代码：DFP
封装等效代码：FL16,.3封装形状：RECTANGULAR
封装形式：FLATPACK并行/串行：PARALLEL
电源：5/15 V认证状态：Not Qualified
筛选级别：MIL-STD-883 Class B (Modified)子类别：SRAMs
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：FLAT端子节距：1.27 mm
端子位置：DUALBase Number Matches：1

MM54C89 数据手册

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March 1988  
MM54C89/MM74C89 64-Bit TRI-STATE  
Random Access Read/Write Memory  
É
General Description  
The MM54C89/MM74C89 is a 16-word by 4-bit random ac-  
cess read/write memory. Inputs to the memory consist of  
four address lines, four data input lines, a write enable line  
and a memory enable line. The four binary address inputs  
are decoded internally to select each of the 16 possible  
word locations. An internal address register latches the ad-  
dress information on the positive to negative transition of  
the memory enable input. The four TRI-STATE data output  
lines working in conjunction with the memory enable input  
provide for easy memory expansion.  
Read Operation: The complement of the information which  
was written into the memory is non-destructively read out at  
the four outputs. This is accomplished by selecting the de-  
sired address and bringing memory enable low and write  
enable high.  
When the device is writing or disabled the output assumes a  
TRI-STATE (Hi-z) condition.  
Features  
Y
Wide supply voltage range  
Guaranteed noise margin  
High noise immunity  
Low power  
3.0V to 15V  
1.0V  
Address Operation: Address inputs must be stable t pri-  
SA  
or to the positive to negative transition of memory enable. It  
is thus not necessary to hold address information stable for  
Y
Y
Y
0.45 V  
CC  
(typ.)  
fan out of 2  
driving 74L  
more than t after the memory is enabled (positive to neg-  
HA  
ative transition of memory enable).  
TTL compatibility  
Y
Y
Y
Low power consumption  
Fast access time  
100 nW/package (typ.)  
e
Note: The timing is different than the DM7489 in that a positive to negative  
transition of the memory enable must occur for the memory to be  
selected.  
130 ns (typ.) at V  
10V  
CC  
TRI-STATE output  
Write Operation: Information present at the data inputs is  
written into the memory at the selected address by bringing  
write enable and memory enable low.  
Logic and Connection Diagrams  
Dual-In-Line Package  
TL/F/5888–2  
Top View  
Order Number MM54C89  
or MM74C89  
TL/F/5888–1  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/5888  
RRD-B30M105/Printed in U. S. A.  
123456

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MM54C89D ROCHESTER

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 		Random Access Read / Write Memory Wide supply voltage range 3.0V ro 15V
MM54C89DB ROCHESTER

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 		Random Access Read / Write Memory Wide supply voltage range 3.0V ro 15V
MM54C89F ROCHESTER

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MM54C89J ROCHESTER

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 		Random Access Read / Write Memory Wide supply voltage range 3.0V ro 15V
MM54C89J NSC

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 		64-Bit TRI-STATE Random Access Read/Write Memory
MM54C89J/883 NSC

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 		IC 16 X 4 STANDARD SRAM, 910 ns, CDIP16, Static RAM
MM54C89J/883 TI

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 		16X4 STANDARD SRAM, 910ns, CDIP16
MM54C89JB ROCHESTER

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 		Random Access Read / Write Memory Wide supply voltage range 3.0V ro 15V
MM54C89J-MIL NSC

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 		IC,SRAM,16X4,CMOS,DIP,16PIN,CERAMIC

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