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MM54C89J/883 PDF预览

MM54C89J/883

更新时间: 2024-09-30 14:53:47
品牌 Logo 应用领域
美国国家半导体 - NSC 静态存储器内存集成电路
页数 文件大小 规格书
6页 20K
描述
IC 16 X 4 STANDARD SRAM, 910 ns, CDIP16, Static RAM

MM54C89J/883 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.41
风险等级:5.88最长访问时间:910 ns
JESD-30 代码:R-CDIP-T16JESD-609代码:e0
长度:19.43 mm内存密度:64 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
功能数量:1端子数量:16
字数:16 words字数代码:16
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:16X4
输出特性:3-STATE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 V认证状态:Not Qualified
筛选级别:MIL-STD-883座面最大高度:5.08 mm
子类别:SRAMs最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MM54C89J/883 数据手册

 浏览型号MM54C89J/883的Datasheet PDF文件第2页浏览型号MM54C89J/883的Datasheet PDF文件第3页浏览型号MM54C89J/883的Datasheet PDF文件第4页浏览型号MM54C89J/883的Datasheet PDF文件第5页浏览型号MM54C89J/883的Datasheet PDF文件第6页 
MICROCIRCUIT DATA SHEET  
Original Creation Date: 10/25/95  
Last Update Date: 05/19/97  
MNMM54C89-X REV 1A0  
Last Major Revision Date: 04/02/97  
64-BIT TRI-STATE RANDOM ACCESS READ/WRITE MEMORY  
General Description  
The MM54C89 is a 16-word by 4-bit random access read/write memory. Inputs to the memory  
consist of four address lines, four data inputs lines, a write enable line and a  
memory enable line. The four binary address inputs are decoded internally to select each  
of the 16 possible word locations. An internal address register latches the address  
information on the positive to negative transition of the memory enable input. The four  
TRI-STATE data output lines working in conjunction with the memory enable input provide  
for easy memory expansion.  
ADDRESS OPERATION: Address inputs must be stable tSA prior to the positive to negative  
transition of memory enable. It is thus not necessary to hold address information stable  
for more than tHA after the memory is enabled (positive to negative transition for  
memory enable).  
Note: The timing is different than the DM7489 in that a positive to negative transition of  
the memory enable must occur for the memory to be selected.  
WRITE OPERATION: Information present at the data inputs is written into the memory at the  
selected address by bringing write enable and memory enable low.  
READ OPERATION: The complement of the information which was written into the memory is  
non-destructively read out at the four outputs. This is accomplished by selecting the  
desired address and bringing memory enable low and write enable high.  
When the device is writing or disabled the output assumes a TRI-STATE (Hi-z) condition.  
Industry Part Number  
NS Part Numbers  
MM54C89  
MM54C89J/883  
Prime Die  
MM54C89  
Processing  
Subgrp Description  
Temp (oC)  
MIL-STD-883, Method 5004  
1
Static tests at  
+25  
2
Static tests at  
+125  
-55  
3
Static tests at  
4
Dynamic tests at  
Dynamic tests at  
Dynamic tests at  
Functional tests at  
Functional tests at  
Functional tests at  
Switching tests at  
Switching tests at  
Switching tests at  
+25  
Quality Conformance Inspection  
5
+125  
-55  
6
MIL-STD-883, Method 5005  
7
+25  
8A  
8B  
9
+125  
-55  
+25  
10  
11  
+125  
-55  
1

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