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MM24128-BRDL5T

更新时间: 2024-11-08 22:40:35
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
19页 119K
描述
256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines

MM24128-BRDL5T 数据手册

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M24256-B  
M24128-B  
C Bus EEPROM  
256/128 Kbit Serial  
I
With Three Chip Enable Lines  
PRELIMINARY DATA  
2
Compatible with I C Extended Addressing  
2
Two Wire I C Serial Interface  
Supports 400 kHz Protocol  
Single Supply Voltage:  
14  
– 4.5V to 5.5V for M24xxx-B  
8
– 2.5V to 5.5V for M24xxx-BW  
– 1.8V to 3.6V for M24xxx-BR  
1
1
Hardware Write Control  
TSSOP14 (DL)  
169 mil width  
PSDIP8 (BN)  
0.25 mm frame  
BYTE and PAGE WRITE (up to 64 Bytes)  
RANDOM and SEQUENTIAL READ Modes  
Self-Timed Programming Cycle  
Automatic Address Incrementing  
Enhanced ESD/Latch-Up Behavior  
100000 Erase/Write Cycles (minimum)  
40 Year Data Retention (minimum)  
8
8
1
1
SO8 (MN)  
150 mil width  
TSSOP8 (DW)  
169 mil width  
DESCRIPTION  
2
These I C-compatible electrically erasable pro-  
grammable memory (EEPROM) devices are orga-  
nized as 32Kx8 bits (M24256-B) and 16Kx8 bits  
(M24128-B).  
Figure 1. Logic Diagram  
These memory devices are compatible with the  
2
I C extended memory standard. This is a two wire  
serial interface that uses a bi-directional data bus  
and serial clock. The memory carries a built-in 4-  
bit unique Device Type Identifier code (1010) in  
V
CC  
2
accordance with the I C bus definition.  
3
E0-E2  
SCL  
WC  
SDA  
Table 1. Signal Names  
M24256-B  
M24128-B  
E0, E1, E2  
SDA  
Chip Enable Inputs  
Serial Data/Address Input/  
Output  
SCL  
WC  
Serial Clock  
Write Control  
Supply Voltage  
Ground  
V
SS  
AI02809  
V
V
CC  
SS  
February 2000  
1/19  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.  

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