FEDL7456N-03
ML7456N
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Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)
Clock stretch function
7bit address format
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I2C bus Master
・ Channel: 1 channel
・ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)
・ Handshake (Clock synchronization)
・ 7bit address format (10bit address format is supported)
General-purpose ports (GPIO)
・ I/O port: Max. 15 (Including one pin for on-chip debug and pins for other shared functions)
・ Input port: Max. 2 (Including a shared function)
・ External interrupt port: Max. 6
・ LED driver port : Max. 12
・ Carrier frequency output function (for IR communication)
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Successive approximation type A/D converter(SA-ADC)
・ Channel: Max. 5 channels
・ Resolution: 10bit
・ Conversion time: Min. 2.25μs/channel (When the conversion clock speed is 8MHz)
・ Reference voltages are selectable
(VDD pin / Internal reference voltage(VREFI = Approximately 1.55V) / External reference voltage (VREF pin) )
・ Selected channel repeat conversion
・ Dedicated result register for each channel
・ Interrupt determining by upper limit or lower limit threshold of conversion result
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Voltage Level Supervisor (VLS)
・ Accuracy: ±4%
・ Threshold voltage: 12 selectable (from 1.85V to 4.00V)
・ Functional Voltage level detection reset (VLS reset)
・ Functional Voltage level detection interrupt (VLS0 interrupt)
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Analog comparator
・ Channel: Max. 2 channels
・ Selectable interrupt from the comparator output (rising edge or falling edge)
・ Comparable with external input and internal reference voltage (0.8V)
D/A converter
・ Channel: Max. 1 channel
・ Resolution: 8bit
・ Output impedance: 6k ohm (Typ.)
・ R-2R ladder type
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Buzzer
・ 4 buzzer mode (Continuous sound, Single sound, Intermittent sound 1 and Intermittent sound 2)
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frequencies (4.096kHz to 293Hz)
・ 15 step duty (1/16 to 15/16)
・ Selectable from positive logic buzzer output or negative logic buzzer output
CRC(Cyclic Redundancy Check) generator
・ Generation equation: X16+X12+X5+1
・ Selectable from LSB first or MSB first
・ Built-in Automatic program memory CRC calculation mode in HALT mode
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