FEDL22Q553-06
ML22Q553-NNN/ML22Q553-xxx
Pin Description (2)
Initial
Attribute
Pin
Symbol I/O Attribute
Description
value(*)
Command processing status signal output pin.
This pin outputs a “L” level during command processing.
Be sure to enter commands with the CBUSYB pin driven
at a “H” level.
Connects to a crystal or a ceramic resonator.
When using an external clock, leave this pin open.
If a crystal or a ceramic resonator is used, connect it as
close to the LSI as possible.
14 CBUSYB
O
O
Negative
Negative
digital
clk
0(*1)
16
XTB
1
Connects to a crystal or a ceramic resonator.
A feedback resistor of around 1 MΩ is built in between this
XT pin and the XTB pin. When using an external clock,
input the clock from this pin.
If a crystal or a ceramic resonator is used, connect it as
close to the LSI as possible.
17
19
XT
I
I
Positive
—
clk
0
0
Pin for FLASH analysis.
Should be connected to DGND.
VPP
analog
Reset input pin.
At “L” level input, the LSI enters the initial state. After a
reset input, the entire circuit is stopped and enters a
power down state. Upon power-on, input a “L” level to
this pin. After the power supply voltage is stabilized,
drive this pin at a “H” level.
20 RESETB
I
Negative
digital
0(*1)
This pin has a pull-up resistor built in.
Input pin for testing. Also acts as a Flash rewrite enable
Positive pin.
Has a pull-down resistor built in.
TESTI0
21
I
digital
0
(MODE)
Used as either an input pin for testing or a reset input pin
for Flash rewriting. Has a pull-down resistor built in.
TESTI1
22
I
I
Negative
Positive
digital
digital
0
1
(nTRST)
Used as either an input pin for testing or a state transition
pin for Flash rewriting. Has a pull-up resistor built in.
TESTI2
23
(TMS)
TESTI3
(TDI)
Used as either an input pin for testing or a data input pin
for Flash rewriting. Has a pull-up resistor built in.
Used as either an input pin for testing or a clock input pin
for Flash rewriting. Has a pull-up resistor built in.
Used as either an output pin for testing or a data output
pin for Flash rewriting.
24
I
I
Positive
Positive
digital
digital
1
1
TESTI4
25
(TCK)
TESTO
26
O
O
Positive
—
digital
Hi-Z
Hi-Z
(TSO)
27
28
29
30
SPM
Output pin of the built-in speaker amplifier.
Output pin of the built-in speaker amplifier.
Can be configured as an AOUT amplifier output by analog
command setting.
analog
SPP
O
—
—
—
—
—
0
SPGND
SPVDD
gnd
—
—
Speaker amplifier ground pin.
Speaker amplifier power supply pin.
Connect a bypass capacitor of 10µF or more between this power
pin and SPGND.
*: Indicates the initial value at reset input or during power down.
*1: “0” during reset. , “1” during power down.
6/71