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MK2743STR PDF预览

MK2743STR

更新时间: 2024-11-21 15:43:11
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
4页 30K
描述
Video Clock Generator, 66MHz, CMOS, PDSO16, 0.150 INCH, SOIC-16

MK2743STR 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.92
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9695 mm端子数量:16
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:66 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
主时钟/晶体标称频率:27 MHz认证状态:Not Qualified
座面最大高度:1.778 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.937 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEO
Base Number Matches:1

MK2743STR 数据手册

 浏览型号MK2743STR的Datasheet PDF文件第2页浏览型号MK2743STR的Datasheet PDF文件第3页浏览型号MK2743STR的Datasheet PDF文件第4页 
MK2743  
ICRO CLOC K C-Cube MPEG Encoder Clock Source  
Description  
Features  
The MK2743 is a low cost, low jitter, high  
performance clock synthesizer designed for  
C-Cube MPEG encoders. Using analog Phase-  
Locked Loop (PLL) techniques, the device accepts  
a 27.00MHz crystal or clock input to produce  
multiple output clocks including the processor  
clock, low skew divides by two and four of the  
processor clock, the audio processor clock, and a  
selectable audio clock. The audio clocks are  
exactly frequency locked to the 27.00MHz input  
with zero ppm error, allowing audio and video to  
track exactly.  
• Packaged in 16 pin narrow (150 mil) SOIC  
• For C-Cube MPEG encoders  
• Selectable audio sampling frequencies support  
32 kHz, 44.1 kHz, and 48 kHz in most DACs  
• 27.00 MHz crystal or clock input  
• Selectable processor frequencies of 60 or 66.0MHz  
• Zero ppm error in audio clocks give highest  
performance audio encoding  
• 25mA output drive capability at TTL levels  
• Advanced, low power, sub-micron CMOS process  
• 5V±10% operating voltage  
MicroClock manufactures the largest variety of  
Set-Top Box and multimedia clock synthesizers  
for all applications. Consult MicroClock to  
eliminate crystals and oscillators from your board.  
Block Diagram  
VDD GND  
2
3
Output  
Buffer  
PCLK  
MPEG  
Processor  
Clocks  
PCS  
Output  
Buffer  
÷ 2  
÷ 4  
PCLK/2  
PCLK/4  
ACLK  
Output  
Buffer  
ACS1  
ACS0  
Audio  
Clock  
Output  
Buffer  
27.00 MHz  
clock or  
crystal  
X1  
Output  
Buffer  
Audio  
Processor  
Clock  
NUCLK  
27.00 MHz  
Input  
Buffer/  
Crystal  
Output  
Buffer  
Oscillator  
X2  
(external capacitors  
needed for crystal input)  
MDS2743B  
1
Revision 12047  
Printed 12/4/97  
MicroClock Division of ICS•1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax  

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