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MK2302S-01 PDF预览

MK2302S-01

更新时间: 2024-09-21 21:55:35
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6页 151K
描述
Multiplier and Zero Delay Buffer

MK2302S-01 数据手册

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MK2302S-01  
Multiplier and Zero Delay Buffer  
Description  
Features  
The MK2302S-01is a high performance Zero Delay  
Buffer (ZDB) which integrates ICS’ proprietary  
8 pin SOIC package  
Low input to output skew of 250ps max  
Absolute jitter ± 500ps  
analog/digital Phase Locked Loop (PLL) techniques.  
The chip is part of ICS’ ClockBlocksTM family and was  
designed as a performance upgrade to meet today’s  
higher speed and lower voltage requirements. The zero  
delay feature means that the rising edge of the input  
clock aligns with the rising edges of both output clocks,  
giving the appearance of no delay through the device.  
There are two outputs on the chip, one being a  
low-skew divide by two of the other output.  
Propagation Delay ± 350ps  
Ability to choose between different multipliers from  
0.5X to 16X  
Output clock frequency up to 133 MHz at 3.3V  
Can recover degraded input clock duty cycle  
Output clock duty cycle of 45/55  
Full CMOS clock swings with 25mA drive capability  
at TTL levels  
The MK2302S-01 is ideal for synchronizing outputs in a  
large variety of systems, from personal computers to  
data communications to graphics/video. By allowing  
off-chip feedback paths, the device can eliminate the  
delay through other devices.  
Advanced, low power CMOS process  
Operating voltage of 3.3V or 5V  
Industrial temperature version available  
Block Diagram  
ICLK  
S1:0  
Phase  
Detector,  
Charge  
Pum p,  
and Loop  
Filter  
VCO  
CLK1  
CLK2  
/2  
divide  
by N  
FBIN  
External feedback can com e from CLK1 or CLK2 (see table on page 2)  
MDS 2302S-01 B  
1
Revision 070803  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 www.icst.com  

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