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MK1728-01GTRLF PDF预览

MK1728-01GTRLF

更新时间: 2024-11-18 21:02:51
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
8页 210K
描述
Clock Generator, 36MHz, CMOS, PDSO8, TSSOP-8

MK1728-01GTRLF 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:TSSOP-8
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84JESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.4 mm
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:36 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED主时钟/晶体标称频率:36 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压:2.625 V最小供电电压:2.375 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

MK1728-01GTRLF 数据手册

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DATASHEET  
2.5 VOLT LOW EMI CLOCK GENERATOR  
MK1728-01  
Description  
Features  
The MK1728-01 generates a low EMI output clock from a  
clock or crystal input. Operating at 2.5 V, the part is  
designed to dither the LCD interface clock for PDAs,  
printers, scanners, modems, copiers, and others. Using  
ICS’ proprietary mix of analog and digital Phase-Locked  
Loop (PLL) technology, the device spreads the frequency  
spectrum of the output, reducing the frequency amplitude  
peaks by several dB. The MK1728-01 offers both centered  
and down spread from a high-speed clock input.  
Operating voltage of 2.5 V  
Packaged in 8-pin SOIC/TSSOP  
Provides a spread spectrum (Center and down spread)  
clock output  
Accepts a clock or crystal input (provides same  
frequency dithered output)  
Input frequency range of 4 to 36 MHz  
Output frequency range of 4 to 36 MHz  
(1X Multiplier)  
ICS offers many other clocks for computers and computer  
peripherals. Consult ICS when you need to remove crystals  
and oscillators from your board.  
Peak reduction by 8 dB to 16 dB typical on 3rd through  
19th odd harmonics  
Low EMI feature can be disabled  
3.3 V tolerant inputs (S0,S1, FRSEL, X1)  
Advanced, low-power CMOS process  
Not recommended for new designs. Use the  
MK1728A-01 for new designs  
Block Diagram  
VDD  
2
S1:0  
PLL Clock  
Synthesis  
and Spread  
FRSEL  
Spectrum  
Circuitry  
SSCLK  
X1/CLK  
X2  
X1  
Clock Buffer/  
Crystal  
Ocsillator  
External caps required with crystal for  
accurate tuning of the clock  
GND  
IDT™ / ICS™ 2.5 VOLT LOW EMI CLOCK GENERATOR  
1
MK1728-01  
REV A 081204  

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